The recommended power-up sequence is to apply VDD first, followed by VCC, and then the analog power supplies (AVDD and DVDD). This ensures that the internal voltage regulators are powered up correctly.
To optimize the analog input impedance, use a series resistor (Rs) and a capacitor (Cs) in parallel with the input signal. The recommended values are Rs = 1 kΩ and Cs = 10 nF. This helps to match the impedance and reduce noise.
The maximum clock frequency for the PCM3008T is 50 MHz. However, the recommended clock frequency is 12.288 MHz for 44.1 kHz sampling rate and 24.576 MHz for 48 kHz sampling rate.
The PCM3008T outputs data in I²S format. The data is transmitted on the SDOUT pin, with the most significant bit (MSB) first. The data is clocked out on the rising edge of the BCK clock signal.
To minimize noise and ensure proper operation, it is recommended to keep the analog and digital power supplies separate, use a solid ground plane, and keep the analog input traces short and away from digital signals.
PCM3008T datasheet
by Texas Instruments
