The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the internal voltage regulators are powered up correctly.
To configure the PCM4202DBT for master clock mode, set the MCLK pin to the desired clock frequency, and set the M/S pin to a logic high. This will enable the internal clock generator.
The maximum input signal level for the ADCs is 2.5 Vrms. Exceeding this level may result in signal distortion or clipping.
To optimize performance in noisy environments, use a low-pass filter on the analog input signals, and consider using a shielded enclosure for the PCB. Additionally, ensure that the power supply lines are well-filtered and decoupled.
The latency of the ADCs is approximately 2.2 clock cycles. This is the time it takes for the ADC to convert an analog input signal to a digital output.
PCM4202DBT datasheet
by Texas Instruments
