The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the internal voltage regulators are powered up correctly.
To configure the PCM4204 for master clock mode, set the MCKI pin to the desired clock frequency, and set the MCKO pin to output the clock signal. Then, set the CLKCFG register to select the internal clock source.
The maximum input signal level for the ADCs is 2.5 Vrms. Exceeding this level may result in distortion or clipping of the input signal.
To optimize performance in noisy environments, use the internal voltage regulators to reduce noise, and consider using external filtering or shielding to reduce electromagnetic interference (EMI).
The latency of the PCM4204's ADCs is approximately 2.2 clock cycles. This means that there is a delay of 2.2 clock cycles between the input signal and the corresponding digital output.
PCM4204PAPT datasheet
by Texas Instruments
