Texas Instruments recommends a 4-layer PCB with a solid ground plane, and to keep the PLL circuitry away from high-frequency signals and noise sources. Additionally, use short traces, and avoid vias and right-angle turns in the signal paths.
Use the PLL1708DBQR's datasheet equations and graphs to determine the optimal values for the loop filter components based on the desired loop bandwidth, phase margin, and damping factor. You can also use TI's PLL Loop Filter Calculator tool to simplify the process.
The PLL1708DBQR can handle input frequencies up to 350 MHz, but the maximum frequency is dependent on the specific application and the quality of the input signal. It's recommended to consult the datasheet and application notes for more information.
The PLL1708DBQR requires a single 3.3V or 2.5V power supply, and it's recommended to use a low-noise, high-PSRR power supply to minimize jitter and ensure optimal performance. Decouple the power pins with 0.1uF and 10uF capacitors, and ensure the power supply can provide the required current.
The typical lock time for the PLL1708DBQR is around 1-2ms, but it can vary depending on the input frequency, loop bandwidth, and other factors. To optimize the lock time, use a narrow loop bandwidth, ensure a clean input signal, and adjust the loop filter components accordingly.
PLL1708DBQR datasheet
by Texas Instruments
