Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    Part Img SN74LS73ADR datasheet by Texas Instruments

    • Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70
    • Original
    • Yes
    • Yes
    • Active
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
    • Powered by Findchips Logo Findchips

    SN74LS73ADR datasheet preview

    SN74LS73ADR Frequently Asked Questions (FAQs)

    • The maximum clock frequency of the SN74LS73ADR is 35 MHz.
    • To ensure proper initialization, connect the preset (PRE) and clear (CLR) inputs to a logic high during power-up. This will set the flip-flops to a known state.
    • The recommended operating voltage range for the SN74LS73ADR is 4.75V to 5.25V.
    • No, the SN74LS73ADR is not designed to operate at 3.3V. It is a 5V device and should only be used in 5V systems.
    • The asynchronous reset (CLR) input should be tied to a logic high during normal operation. When CLR is low, the flip-flops are reset to a logic low state.
    Supplyframe Tracking Pixel