The recommended power-on sequence is to power up the core voltage (VDD_CORE) first, followed by the I/O voltage (VDD_IO). This ensures that the internal voltage regulators are properly enabled.
The DM365 uses a PLL-based clocking system. The PLL is configured through the PLL Control Register (PLLCTL). The clock frequency can be set using the Clock Frequency Register (CLKFREQ).
The maximum operating frequency of the DM365 is 300 MHz. However, the actual operating frequency may be limited by the specific application and the clock configuration.
The EMIF is configured through the EMIF Control Register (EMIFCTL). The EMIF supports asynchronous and synchronous modes, and can be used to interface with external memory devices such as DDR2, DDR3, and asynchronous SRAM.
The ARM core is used for general-purpose processing and running the operating system, while the DSP core is used for digital signal processing tasks such as video and image processing.
TMS320DM365ZCE30 datasheet
by Texas Instruments
