The recommended power-up sequence is to apply power to the core voltage (VDD_CORE) first, followed by the I/O voltage (VDD_I/O). This ensures that the internal voltage regulators are powered up correctly.
To configure the EMIF for optimal performance, ensure that the memory timing parameters (e.g. CAS latency, RAS-to-CAS delay) are set correctly, and that the memory clock frequency is within the recommended range (133 MHz to 166 MHz).
The maximum frequency of the ARM core is 729 MHz. To achieve this frequency, ensure that the clock source is set to the internal oscillator, and that the PLL (Phase-Locked Loop) is configured correctly. Additionally, ensure that the power management settings are optimized for high-performance mode.
To use the EDMA controller, configure the EDMA channels to transfer data between peripherals and memory. Set up the EDMA transfer parameters (e.g. transfer size, source/destination addresses) and enable the EDMA channel. The EDMA controller will then handle the data transfer, reducing the load on the ARM core.
The Reset pin is used to reset the device and return it to its default state. To use the Reset pin, connect it to a reset source (e.g. a push-button or a reset generator) and ensure that the reset signal is asserted for at least 10 ns to ensure a proper reset.