The recommended power-up sequence is to apply VDD first, followed by VDDA, and then the digital supplies (VDDIO and VDDC). This ensures that the analog and digital sections of the device are powered up in a controlled manner.
To optimize the performance of the WM8740EDS in terms of THD+N, ensure that the device is operated within the recommended operating conditions, use a high-quality clock source, and optimize the analog and digital filter settings. Additionally, ensure that the PCB layout is optimized to minimize noise and interference.
The maximum clock frequency that can be used with the WM8740EDS is 256fs, where fs is the sampling frequency. However, it is recommended to use a clock frequency of 128fs or lower to ensure optimal performance and minimize jitter sensitivity.
To configure the WM8740EDS for master clock mode, set the MCLK pin to the desired clock frequency, and ensure that the BCLK pin is tied to the MCLK pin. Additionally, set the LRCK pin to the desired frame rate, and configure the serial data interface to use the desired data format (e.g. I2S, DSP, or TDM).
The recommended decoupling capacitor configuration for the WM8740EDS is to use a 10uF capacitor in parallel with a 100nF capacitor, connected between the VDD pin and the GND pin. This helps to filter out noise and ensure stable power supply to the device.
