The recommended power-up sequence is to apply VDD first, followed by VDDIO, and then the clock signal. This ensures proper initialization of the device.
To configure the WM8750 for master clock mode, set the MCLK pin as an output by setting the MCLKOE bit in the Clock Control Register (CKCNTRL). Then, set the desired clock frequency using the MCLKDIV and MCLKFRQ registers.
The digital mute pin (DMUTE) is used to mute the digital audio output. When DMUTE is high, the digital audio output is muted, and when it's low, the output is enabled.
To optimize power consumption, use the Power Management Register (PWRCNTRL) to control the power-down modes of the device. Additionally, use the Dynamic Voltage and Frequency Scaling (DVFS) feature to adjust the clock frequency and voltage supply based on the system's requirements.
The maximum allowed capacitance for the WM8750's analog inputs is 10nF. Exceeding this value may affect the device's performance and stability.
WM8750CBLGEFL datasheet
by Cirrus Logic
