DSAH00133465.pdf by Cypress Semiconductor

Partial File Text CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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