DSA00388689.pdf
by Xilinx

Partial File Text Virtex-6 FPGA Configurable Logic Block User Guide Virtex-6 FPGA CLB [optional] UG364 (v1.0) June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or speci
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DPRAM32 DSP48E DSP48E1 RAM128X1D RAM32M ROM64x1 shift register by using D flip-flop SRLC32E virtex 6 XC6VSX475T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX75T XC6VLX760 XC6VSX475T