DSASDKL1000909.pdf by Silicon Laboratories

Partial File Text C8051F060/1/2/3/4/5/6/7 Mixed Signal ISP Flash MCU Family High Speed 8051 ÂµC Core - Pipelined instruction architecture; executes 70% of Analog Peripherals - Two 16-Bit SAR ADCs â¢ 16-bit res
Datasheet Type Original
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Pb Free Unknown
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