000505B Search Results

Contextual Info: 1.0 I n t r o d u c t io n 1.1.3 Circular Buffers The monolithic SUMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SUMMIT is a single-chip device that implements all three of the defined MIL-STD-1553 functions Remote Terminal, Bus Controller, and Monitor. Operating

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SIS 661

Abstract: VM009 CA95C68 CA95C18 CA95C09 AM9518 AM9568 SDS S4 24V Z8000 nb11c
Contextual Info: NEWBRIDGE MICROSYSTEMS NEWBRIDGE MICROSYSTEMS =,4E D JANUARY 1993 • bSflfilOl DQOSQSS 35S ■ NBMC CA95C68/18/09 DES DATA CIPHERING PROCESSORS (DCP • Encrypts/Decrypts data using National Bureau of Standards Data Encryption Standard (DES) • High speed, pin and function compatible version

83C154D-16

Abstract: 83C154D-20
Contextual Info: Tem ic 83C154D MATRA MHS CMOS 0 to 30 MHz Single-Chip 8 Bit Microcontroller Description The MHS 83C154D retains all the features of the MHS 80C52 with extended ROM capacity 32 K bytes , 256 bytes of RAM, 32 I/O lines, a 6-source 2-level interrupts, a full duplex serial port, an on-chip oscillator and clock

Contextual Info: HY5216256 Series -HYUNDAI 256Kx 16-bit Video RAM with 2CAS Introduction Overview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.

photodiode Responsivity

Abstract: PIN photodiode responsivity 1550nm 2,5 GHz FRM15w PIN Photodiode 1550nm 4 ghz
Contextual Info: • FHNH5W23WH D ES C R IP TIO N The FR M 15W 231C R is an APD pre-amplifier module for 1550nm wave­ length optical receiver front-end. It contains a planar InGaAs-APD Avalanche Phto-diode and a transimpedance type GaAs pre-amplifier IC. The InGaAs-APD, having high responsivity, low capacitance and low noise

IR 448H

Abstract: GR-1400 446H PDI 45A BPT T41 C02h ir 446h lm 741 using schmitt trigger PSL 26 PM5344
Contextual Info: PMC-Sierra, Inc. S TANDARD PRO DUCT PM C -951010 IS S U E 4 PM5362 TUPP-PLUS SONET/SDH TRIBUTARY U NIT PAYLOAD PROCESSOR FEA TU R ES • Configurable, multi-channel, payload processor for aligning SONET virtual tributaries VTs or SDH tributary units (TUs) in an STS-3 or STM-1 byte serial

CU01C

Abstract: 5962-8751410 AT28HC64-70 28HC64 A12C AT28HC64
Contextual Info: AT28HC64/L Features • • Fast Read Access Time - 55 ns Automatic Page Write Operation Internal Address and Data Latches for 32 Bytes Internal Control Timer • Fast Write Cycle Times Maximum Page Write Cycle Time: 2 ms 1 to 32 Byte Page W rite Operation

Contextual Info: GAL6001 Lattice High Performance E2CMOS FPLA Generic Array Logic Semiconductor • ■ ■ ■ Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOG Y — 30ns Maxim um Propagation Delay — 27MHz Maxim um Frequency — 12ns Maxim um Clock to Output Delay

NAIS 414

Abstract: 7 segment 5165
Contextual Info: NJU6423B 20-CHARACTER 2-LIN E DOT M A T R I X LCD CONTROLLER D R IV E R • GENERAL DESCRIPTION The NJUS423B is a 1 Chip Dot Matrix LCD controller driver for up to 20-character 2-1ine display. It contains voltage converter, bleeder resistance, CR oscillator, microprocessor interface circuits, instruc­

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373MTCX 74LVX373MX 74LVX373SJ 74LVX373SJX
Contextual Info: LVX373 National Semiconductor 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs General Description Features The LVX373 consists of eight latches with TRI-STATE out­ puts for bus organized system applications. The latches ap­ pear transparent to the data when Latch Enable LE is

marking code 50Z

Abstract: smd marking code ADOR
Contextual Info: REVISIONS LTR DESCRIPTION DATE Redrawn with changes. Added device types 19 through 22. Added vendor CAGE 65786 for device types 19 and 20. Added vendor CAGE 61772 for devices 21 and 22. Corrected errors to Table I. Added pin 1 reference to case outline U.

R1C11

Abstract: r6c1
Contextual Info: Configuration selection generates starting addresses at either zero or 3FFFF, to be compatible with different microprocessor addressing conventions. The Master Serial Mode generates CCLK and receives the configuration data in serial form from configuration data in serial form from a