001AAI139 Search Results

HEF4081BP

Abstract: HEF4081BT HEF4081B MO-001
Contextual Info: HEF4081B Quad 2-input AND gate Rev. 05 — 29 June 2009 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

Contextual Info: HEF4081B-Q100 Quad 2-input AND gate Rev. 1 — 13 November 2013 Product data sheet 1. General description The HEF4081B-Q100 is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.

Contextual Info: HEF4081B Quad 2-input AND gate Rev. 7 — 16 November 2011 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.

HEF4081B

Abstract: HEF4081BP The HE4000B Logic Family Specification DIP14 package HEF4081BT HEF4081BT JESD22-A114E MO-001
Contextual Info: HEF4081B Quad 2-input AND gate Rev. 04 — 26 May 2008 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

HEF4081BP

Abstract: HEF4081BT HEF4081B MO-001 HEF4081 HEF40 001aai139 HEF4081BC
Contextual Info: HEF4081B Quad 2-input AND gate Rev. 06 — 2 December 2009 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.

Contextual Info: HEF4081B Quad 2-input AND gate Rev. 7 — 16 November 2011 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.