0DLB23FI Search Results

Contextual Info: D S1004 n A I I A C DS1004 5-Tap High-Speed Silicon Delay Line s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, +0.75, or ±1 ns