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    Untitled

    Abstract: No abstract text available
    Text: ¡ET Preliminary Commercial INC. PEEL 20V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features Compatible with Popular 20V8 Devices — 20V8 socket and function compatible — Programs with standard 20V8 JEDEC file — 24-pin DIP/SOIC, 28-pin PLCC packages


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    PDF 24-pin 28-pin 0G01bfi3 40-Pin

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Commercial IN C . PEEL 22CV1 OAZ -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 133 product term x 44 input AND array — Up to 22 inputs and 10 I/O pins — 12 possible macrocell configurations


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    PDF 22CV1 24-pin 28-pin 25jiA 0G01bfi3 40-Pin 0001bfl4

    Untitled

    Abstract: No abstract text available
    Text: Commercial/ Industrial INC. TM PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features I CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP and 44-pin PLCC packages I Versatile Logic Array Architecture - 24 l/Os, 14 inputs, 60 registers/latches


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    PDF PA7140 40-pin 44-pin 13ns/2Plastic 28-Pin 004-J 0G01bfi3 0001bfl4

    Untitled

    Abstract: No abstract text available
    Text: Commercial/ Industrial INC. PEEL 22CV10A -5/-7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Features High Speed/Low Power — Speeds ranging from 5ns to 25ns — Power as low as 67mA at 25MHz Architectural Flexibility — 132 product term X 44 input AND array


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    PDF 22CV10A -5/-7/-10/-15/L-15/-25 25MHz 24-pin 28-pin 22V10 Enhanc28) 0G01bfi3

    PEEL20CG10AJ-15

    Abstract: No abstract text available
    Text: Commercial/ Industrial INC.- PEEL 20CG10A -5/-7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Features Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Up to 12 configurations per macrocell


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    PDF 20CG10A -5/-7/-10/-15/L-15/-25 24-pin 28-pin 25MHz 0G01bfi3 40-Pin 0001bfl4 PEEL20CG10AJ-15