1.9 TDI VOLTAGE REGULATOR Search Results

CY7C1302DV25

Abstract: CY7C1302DV25-167 3M Touch Systems
Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■

3M Touch Systems

Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■

CY7C1303BV25

Abstract: CY7C1306BV25 3M Touch Systems
Contextual Info: CY7C1303BV25 CY7C1306BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions

3M Touch Systems

Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

3M Touch Systems

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Functional Description Features • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■

3M Touch Systems

Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■

Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■

3M Touch Systems

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

Contextual Info: MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D − Active Mode: 280 µA at 1 MHz, 2.2 V

Contextual Info: MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D − Active Mode: 280 µA at 1 MHz, 2.2 V

Contextual Info: MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D − Active Mode: 280 µA at 1 MHz, 2.2 V

Contextual Info: MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D − Active Mode: 280 µA at 1 MHz, 2.2 V

Contextual Info: SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES SCAS190E – JUNE 1990 – REVISED JANUARY 1997 D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard

tbc 541

Abstract: ACT8990 SN54ACT8990 SN74ACT8990
Contextual Info: SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES SCAS190E – JUNE 1990 – REVISED JANUARY 1997 D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard

MSP430

Abstract: MSP430C1331 MSP430C1331IPM MSP430C1351 MSP430C1351IPM
Contextual Info: MSP430C13x1 MIXED SIGNAL MICROCONTROLLER SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D On-Chip Comparator D Serial Communication Interface USART , − Active Mode: 160 µA at 1 MHz, 2.2 V

5962R0922501VXC

Abstract: 5962R0922501QXC ISL70001SRHF ISL70001SRHVF ISL70001SRH Lxx 05 smd TB363 4060 SYNCHRONOUS COUNTER EQ122 1.9 TDI Voltage Regulator
Contextual Info: ISL70001SRH Features The ISL70001SRH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output

Contextual Info: MSP430C13x1 MIXED SIGNAL MICROCONTROLLER SLAS341C − SEPTEMBER 2001 − REVISED DECEMBER 2008 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow Power Consumption: D D D D D D On-Chip Comparator D Serial Communication Interface USART , − Active Mode: 160 µA at 1 MHz, 2.2 V

MSP430

Abstract: MSP430C1331 MSP430C1331IPM MSP430C1351 MSP430C1351IPM
Contextual Info: MSP430C13x1 MIXED SIGNAL MICROCONTROLLER SLAS341C − SEPTEMBER 2001 − REVISED DECEMBER 2008 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow Power Consumption: D D D D D D On-Chip Comparator D Serial Communication Interface USART , − Active Mode: 160 A at 1 MHz, 2.2 V

Contextual Info: WM2200 w Low Power CODEC with Enhanced Wolfson myZone Ambient Noise Cancellation DESCRIPTION FEATURES The WM2200 is a low power mobile CODEC with enhanced TM Wolfson myZone Ambient Noise Cancellation ANC . It is ideal for mobile telephony applications, providing enhanced

vqg44

Contextual Info: XA2C64A CoolRunner-II Automotive CPLD R DS553 v1.0 October 31, 2006 Features • • • • • • AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade Guaranteed to meet full electrical specifications over

ACT8990

Abstract: SN54ACT8990 SN74ACT8990 scas190e
Contextual Info: SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES SCAS190E – JUNE 1990 – REVISED JANUARY 1997 D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard

SN74ACT8990FNR

Contextual Info: SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES SCAS190E – JUNE 1990 – REVISED JANUARY 1997 D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard