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CY7C1302DV25 Price and Stock

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Rochester Electronics LLC CY7C1302DV25-167BZC IC SRAM 9MBIT PAR 167MHZ 165FBGA
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DigiKey	CY7C1302DV25-167BZC	Tray	775		10	1 - 10 $30.04 100 $30.04 1000 $30.04 10000 $30.04	Buy Now
Rochester Electronics LLC CY7C1302DV25-167BZXC IC SRAM 9MBIT PAR 167MHZ 165FBGA
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DigiKey	CY7C1302DV25-167BZXC	Tray	20		10	1 - 10 $30.04 100 $30.04 1000 $30.04 10000 $30.04	Buy Now
Infineon Technologies AG CY7C1302DV25-167BZC IC SRAM 9MBIT PAR 167MHZ 165FBGA
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DigiKey	CY7C1302DV25-167BZC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Infineon Technologies AG CY7C1302DV25-167BZXC IC SRAM 9MBIT PAR 167MHZ 165FBGA
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DigiKey	CY7C1302DV25-167BZXC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Avnet Americas	CY7C1302DV25-167BZXC	Tray		0 Weeks, 2 Days	33	1 - 10 - 100 $19.68122 1000 $19.06762 10000 $19.06762	Buy Now
FLIP ELECTRONICS CY7C1302DV25-167BZXC IC SRAM 9MBIT PAR 167MHZ 165FBGA
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DigiKey	CY7C1302DV25-167BZXC	Tray			25	1 - 10 - 100 $20.46 1000 $20.46 10000 $20.46	Buy Now

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CY7C1302DV25 Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF	PDF Size	Page count
CY7C1302DV25		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	219.88KB	18
CY7C1302DV25-100		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	221.48KB	18
CY7C1302DV25-100BZXC		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	219.88KB	18
CY7C1302DV25-133		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	221.48KB	18
CY7C1302DV25-167		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	221.47KB	18
CY7C1302DV25-167BZC		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	391.84KB	18
CY7C1302DV25-167BZXC		Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture		Original	PDF	391.84KB	18

CY7C1302DV25 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1302DV25 Abstract: CY7C1302DV25-167 3M Touch Systems Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■	Original	CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 3M Touch Systems	PDF
CY7C1302DV25 Abstract: CY7C1302DV25-167 5N25 Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 5N25	PDF
CY7C1302DV25 Contextual Info: CY7C1302DV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time	Original	CY7C1302DV25 167-MHz CY7C1302DV25	PDF
CY7C1302DV25 Abstract: CY7C1302DV25-167 Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167	PDF
Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Functional Description Features • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■	Original	CY7C1302DV25 167-MHz	PDF
3M Touch Systems Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■	Original	CY7C1302DV25 CY7C1302DV25 3M Touch Systems	PDF
Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■	Original	CY7C1302DV25 167-MHz	PDF
3M Touch Systems Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■	Original	CY7C1302DV25 CY7C1302DV25 3M Touch Systems	PDF
3M Touch Systems Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■	Original	CY7C1302DV25 CY7C1302DV25 3M Touch Systems	PDF
CY7C1302DV25 Abstract: CY7C1302DV25-167 Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167	PDF