1024X18 Search Results

Contextual Info: CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024x18 IDT72805LB IDT72815LB IDT72825LB • Enable puts output data bus in high impedance state • High-performance submicron CMOS technology • Available in a 121-lead, 1 6 x 1 6 mm plastic Ball Grid

Contextual Info: CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024x18 PRELIMINARY IDT72805LB IDT72815LB IDT72825LB • Enable puts output data bus in high impedance state • High-performance submicron CMOS technology • Available in a 121-lead, 1 6 x 1 6 mm plastic Ball Grid

Contextual Info: CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024x18 d ty IDT72805LB IDT72815LB IDT72825LB Integrated Device Technology, Inc. • Enable puts output data bus in high impedance state • High-performance submicron CMOS technology • Available in a 121-lead, 1 6 x 1 6 mm plastic Ball Grid

72511L5

Contextual Info: bôE D m tia s s ? ? ! PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024x18 o d ^ g i ? m • id t IDT72511 IDT72521 I N T E G R A T E D DEVICE. Integrated Device Technology» Inc. FEATURES: DESCRIPTION: • Two side-by-side FIFO memory arrays for bidirectional

Contextual Info: PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024x18 IDT72511 IDT72521 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Two side-by-side FIFO m em ory arrays for bidirectional data transfers • 512 x 18-Bit - 512 x 18-Bit IDT72511 • 1024 x 18-Bit -1 0 2 4 x 18-Bit (IDT72521 )

BOX655303

Abstract: SN74ACT7802
Contextual Info: SN74ACT7802 1024x18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS187B - A U G U ST 1990 - REVISED S EPTEM B ER 1995 Fast Access Times of 30 ns With a 50-pF Load Fall-Through Time Is 20 ns Typical Data Rates From 0 to 40 MHz High-Output Drive for Direct Bus Interface

Contextual Info: 256 x 1 8: PDM42205 5 12x18: PDM42215 1024x18: PDM42225 Paradigm CMOS High Speed Synchronous FIFOs 256 x 18-Bit to 1024 x 18-Bit Features Description I H igh speed access times Com 'l: 10,15, 20, 25, 30,50 ns Ind.: 15, 20, 25, 30, 50 ns Clock synchronous interface for high speed

clocked RS flip flop

Contextual Info: APR 2« iS«? PARADIGM P R E L IM IN A R Y CMOS HIGH SPEED SYNCHRONOUS FIFOS 256 X 18-BIT TO 1024 X 18-BIT 256X18 512X18 1024X18 PDM42205 PDM 42215 PDM42225 FEATURES • • • • • • • 256 x 18 through 1024 x 18 FIFO Family Clock Synchronous Interface for High Speed

Contextual Info: MOSEL MS76215 & MS76225 ADVANCE INFORMATION 512 x 18 & 1024x18 Parallel Synchronous FIFOs FEATURES DESCRIPTION • Full C M O S clocked synchronous FIFO s The MS76215 and MS76225 are clocked registered FIFOs that are particularly useful in synchronous design applications. This

DAs 08

Abstract: em 495 b12
Contextual Info: PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024x18 IDT72511 IDT72521 In te g r a t e d D e v ic e T e c h n o lo g y , Inc. FEATURES: DESCRIPTION: • Two side-by-side FIFO memory arrays for bidirectional data transfers • 512 x 18-Bit -5 1 2 x 18-Bit IDT72511

Contextual Info: PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024x18 IDT72511 IDT72521 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Two side-by-side FIFO memory arrays for bidirectional data transfers • 512 x 18-Bit - 512 x 18-Bit IDT72511 • 1024 x 18-Bit -1024 x 18-Bit (IDT72521)

D1302

Contextual Info: MOSEL MS72215/16 & MS72225/26 ADVANCE INFORMATION 512 x 18 & 1024x18 Parallel Synchronous FIFOs FEATURES DESCRIPTION • Full C M O S clocked synchronous FIFO s The MS72215/16 and MS72225/26 are clocked registered FIFOs that are particularly useful in synchronous design applications.

Contextual Info: 256 x 18: PDM42205 5 1 2 x 1 8 : PDM42215 1024x18: PDM42225 Paradigm ' b^m o^D DDOOMbö a m m p k i CMOS High Speed Synchronous FIFOs 256 x 18-Bit to 1024 x 18-Bit Features Description □ H igh sp eed access times Com 'l: 1 0 ,1 5 ,2 0 ,2 5 ,3 0 ,5 0 ns Mil: 1 5 ,2 0 ,2 5 ,3 0 ,5 0 ns

SN74ACT7811

Abstract: SN74ACT7881 SN74ACT7882 SN74ACT7884
Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227A- FEBRUARY 1993 - REVISED JUNE 1994 Member of the Texas Instruments Wldebus Family * Input-Ready, Output-Ready, and Half-Full Flags Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

rs-flip-flop

Abstract: Metastabili SN74ABT7819 SN74ACT7801 SN74ACT7807 SN74ACT7811 SN74LS224A SN74S225 Schieberegister Lesen Sie mehr!
Contextual Info: EB 201 FIFOs Architektur, Funktion, Einsatz Verfasser: Peter Forstner Datum: 10.12.91 Rev.: 1.1 Der vorliegende Bericht befaßt sich eingehend mit den FIFO Bausteine von TEXAS INSTRUMENTS . Der erste Teil stellt die Einteilung der FIFOs nach ihrer Funktionalität in die verschiedenen Arten vor. Im zweiten Teil werden die heute

synchronous fifo

Abstract: fifo "digital delay line" 201E SN74ABT7819 SN74ACT7801 SN74ACT7807 SN74ACT7811 SN74S225
Contextual Info: EB 201E FIFOs Architecture, Functions, Application Author: Peter Forstner Date: 10.12.91 Rev.: 1.1 This report takes a detailed look at FIFO devices from TEXAS INSTRUMENTS . The first part presents the different functions of FIFOs and the resulting types that are

AR-17

Abstract: AW12 Q110 Q117 RAM1024 scuba ar17
Contextual Info: ORCA Series 4 Quad-Port Embedded Block RAM August 2002 Technical Note TN1016 Introduction The ORCA Series 4 FPGA platform provides embedded block RAM EBR macrocells to compliment it’s distributed PFU RAM. By using ORCA Series 4 EBR, designers can realize the benefits of system-on-a- chip (SoC) and

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.1EA, February 2012 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

pt45

Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

Contextual Info: PARADIGM Product Family MODULES Secondary Level Cache Modules Static RAM Modules • • • • • • • • PDM4M096S PDM4M096L PDM4M4030 PDM4M4040 PDM4M4050 PDM4M4060 PDM4M4110 PDM4M4120 512K x 8 Asynchronous (512K x 8 Asynchronous) (64Kx 32 Asynchronous)

IDT72205LB

Abstract: IDT72805LB IDT72815LB IDT72825LB 72815
Contextual Info: CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18 IDT72805LB IDT72815LB IDT72825LB Integrated Device Technology, Inc. • Enable puts output data bus in high impedance state • High-performance submicron CMOS technology • Available in a 121-lead, 16 x 16 mm plastic Ball Grid

MI0805K400R-10

Abstract: QL1P1000 QL1P600 LVCMOS25 PS324
Contextual Info: QuickLogic PolarPro® Device Data Sheet — QL1P600 and QL1P1000 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  80 quad clock networks per device Low Power Programmable Logic

32-PIN

Abstract: LH540202
Contextual Info: SHARp ^ blE ]> • i w ^ / m o m ô i a Q ? DG1D1MD 6Bb « S R P J /no p r e li m i n a r y I / U 4 - CMOS 5 1 2 x 9 / 1 0 2 4 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-ln, First-Out mem­