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    128M32 Price and Stock

    Alliance Memory Inc AS4C128M32MD2A-18BIN

    IC DRAM 4GBIT PARALLEL 134FBGA
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    DigiKey AS4C128M32MD2A-18BIN Tray 3,733 1
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    Mouser Electronics AS4C128M32MD2A-18BIN 135
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    Newark AS4C128M32MD2A-18BIN Bulk 168 1
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    TME AS4C128M32MD2A-18BIN 1
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    Karl Kruse GmbH & Co KG AS4C128M32MD2A-18BIN 8,474
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    Micron Technology Inc MT53E128M32D2DS-053-AIT:A

    IC DRAM 4GBIT 1.866GHZ 200WFBGA
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    DigiKey MT53E128M32D2DS-053-AIT:A Tray 2,971 1
    • 1 $10.77
    • 10 $9.556
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    Micron Technology Inc MT53E128M32D2DS-053-WT:A

    IC DRAM 4GBIT 1.866GHZ 200WFBGA
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    DigiKey MT53E128M32D2DS-053-WT:A Tray 2,377 1
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    Micron Technology Inc MT53E128M32D2DS-053-AAT:A

    IC DRAM 4GBIT 1.866GHZ 200WFBGA
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    DigiKey MT53E128M32D2DS-053-AAT:A Tray 1,938 1
    • 1 $11.26
    • 10 $10.426
    • 100 $8.9215
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    Micron Technology Inc MT53E128M32D2DS-046-AAT:A

    IC DRAM 4GBIT 2.133GHZ 200WFBGA
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    DigiKey MT53E128M32D2DS-046-AAT:A Tray 626 1
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    128M32 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    216-ball

    Abstract: Dual LPDDR2 LPDDR2 SDRAM micron LPDDR2 1Gb Memory MT42L128M64D4 MR63 Micron LPDDR2 lpddr2 168 lp-ddr2 MT42L256M32
    Text: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, 128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


    Original     		PDF MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 09005aef83f3f2eb 216-ball Dual LPDDR2 LPDDR2 SDRAM micron LPDDR2 1Gb Memory MR63 Micron LPDDR2 lpddr2 168 lp-ddr2 MT42L256M32

    Lpddr2 Idd7

    Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1
    Text: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle


    Original     		PDF 512Mb NT6SM16M32AK -16Meg -90-ball x13mm) 16M32 Lpddr2 Idd7 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1

    M1012

    Abstract: No abstract text available
    Text: 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, 128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 Features Options • VDD2: 1.2V • Configuration – 32 Meg x 16 x 8 banks x 1 die – 16 Meg x 32 x 8 banks x 1 die


    Original     		PDF MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 134-ball 168-ball 216-ball M1012

    Untitled

    Abstract: No abstract text available
    Text: Preliminary‡ 4Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Features Automotive Mobile LPDDR2 SDRAM MT42L256M16D1, 128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 Features Options • VDD2: 1.2V • Configuration – 32 Meg x 16 x 8 banks x 1 die


    Original     		PDF MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 134-ball 168-ball 09005aef84427aab)

    mt42l128M32

    Abstract: mt42l256m32 MT42L64M32D1 LPDDR2-1066 MT42L256M32D4 MT42L128M32D MT42L128M16D1 MT42L128M64D4 MT42L256M32D MT42L128M32D2
    Text: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, 128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


    Original     		PDF MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 09005aef83f3f2eb mt42l128M32 mt42l256m32 MT42L64M32D1 LPDDR2-1066 MT42L256M32D4 MT42L128M32D MT42L128M16D1 MT42L256M32D MT42L128M32D2

    MT42L64M64D2

    Abstract: mt42l128M32 LPDDR2-1066 64M32 MT42L128M64D4 MT42L MT42L256M32D4 MT42L64M32D1 LPDDR2 SDRAM micron micron lpddr2
    Text: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, 128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


    Original     		PDF MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 09005aef83f3f2eb MT42L64M64D2 mt42l128M32 LPDDR2-1066 64M32 MT42L MT42L256M32D4 MT42L64M32D1 LPDDR2 SDRAM micron micron lpddr2

    MT42L256M32D2

    Abstract: LPDDR2 SDRAM micron MT42L128M32D1 PS 229 ADQ-22 micron lpddr2 MT42L256M32D marking wl4 SMD MARKING code 4N Dual LPDDR2
    Text: 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, 128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 Features Options • Ultra low-voltage core and I/O power supplies – VDD2 = 1.14–1.30V


    Original     		PDF MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 09005aef84427aab MT42L256M32D2 LPDDR2 SDRAM micron MT42L128M32D1 PS 229 ADQ-22 micron lpddr2 MT42L256M32D marking wl4 SMD MARKING code 4N Dual LPDDR2

    lpddr2 256mb

    Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2
    Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ


    Original     		PDF 256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 lpddr2 256mb NT6DM8M32AC-T1 NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2

    lpddr2 DQ calibration

    Abstract: micron lpddr2 lpddr2-s4 ADQ28 MT42L128M16D1 LPDDR2 SDRAM micron MT42L64M32D1 MT42L128M32D2 mt42l256m32 LPDDR2 1Gb Memory
    Text: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, 128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


    Original     		PDF MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 09005aef83f3f2eb lpddr2 DQ calibration micron lpddr2 lpddr2-s4 ADQ28 MT42L128M16D1 LPDDR2 SDRAM micron MT42L64M32D1 MT42L128M32D2 mt42l256m32 LPDDR2 1Gb Memory

    LPDDR2 SDRAM micron

    Abstract: lpddr2 MT42L256M32D2 LPDDR2 SDRAM micron lpddr2 MT42L128M32D1 micron LPDDR2 X32 35MR11 lpddr2 DQ calibration 216-ball LPDDR
    Text: 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, 128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 Features Options • Ultra low-voltage core and I/O power supplies – VDD2 = 1.14–1.30V


    Original     		PDF MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 09005aef84427aab LPDDR2 SDRAM micron lpddr2 MT42L256M32D2 LPDDR2 SDRAM micron lpddr2 MT42L128M32D1 micron LPDDR2 X32 35MR11 lpddr2 DQ calibration 216-ball LPDDR

    MT46H64M32

    Abstract: MT46H128 MT46H64M32L2CG-6 MT46H128M 152-Ball lpddr MT46H128M32 micron lpddr 128M32 MT46H128M32L4KZ
    Text: 152-Ball x32 Mobile LPDDR only PoP (TI-OMAP) Features Mobile LPDDR (only) 152-Ball Package-on-Package (PoP) TI-OMAP MT46HxxxMxxLxCG MT46HxxxMxxLxKZ Features Options • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR)


    Original     		PDF 152-Ball MT46HxxxMxxLxCG MT46HxxxMxxLxKZ 09005aef833913f1/Source: 09005aef833913d6 MT46H64M32 MT46H128 MT46H64M32L2CG-6 MT46H128M lpddr MT46H128M32 micron lpddr 128M32 MT46H128M32L4KZ

    Lpddr2 Idd7

    Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2
    Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle


    Original     		PDF 256Mb NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 Lpddr2 Idd7 Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2

    NT6DM32M16AD-T1

    Abstract: NT6DM32M16AD NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout
    Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver


    Original     		PDF 512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball NT6DM32M16AD-T1 NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout

    NTC 200-9

    Abstract: a2240 128M16 A1930 NT6SM16M32
    Text: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle


    Original     		PDF 512Mb NT6SM16M32AK -16Meg 16M32 NTC 200-9 a2240 128M16 A1930 NT6SM16M32

    Micron Technology automotive

    Abstract: No abstract text available
    Text: 2Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks MT46H64M32LF – 16 Meg x 32 x 4 Banks 128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4 Features Options • VDD/VDDQ = 1.70–1.95V


    Original     		PDF MT46H128M16LF MT46H64M32LF MT46H128M32L2 MT46H256M32L4 09005aef8541eee0 Micron Technology automotive

    hynix lpddr2

    Abstract: Elpida LPDDR2 Memory elpida lpddr2 ELPIDA mobile dram LPDDR2 lpddr2 spec lpddr2 spec HYNIX LPDDR2 1Gb Memory LPDDR2 SDRAM hynix hynix lpddr2 sdram samsung lpddr2
    Text: 512Mb LPDDR2-S4 SDRAM NT6TL16M32AQ/ NT6TL32M16AQ Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS,  is transmitted/received with data, to be used in capturing data at the receiver 


    Original     		PDF 512Mb NT6TL16M32AQ/ NT6TL32M16AQ hynix lpddr2 Elpida LPDDR2 Memory elpida lpddr2 ELPIDA mobile dram LPDDR2 lpddr2 spec lpddr2 spec HYNIX LPDDR2 1Gb Memory LPDDR2 SDRAM hynix hynix lpddr2 sdram samsung lpddr2

    NT6DM16M16AD-T1

    Abstract: 64M32 HP 3458 NT6DM16M16AD-T1I
    Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ


    Original     		PDF 256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 NT6DM16M16AD-T1 64M32 HP 3458 NT6DM16M16AD-T1I

    LPDDR 8Gb

    Abstract: lpddr2 256mb NT6DM32M16AD-T1 NT6DM32M16AD nanya lpddr2 spec
    Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver


    Original     		PDF 512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball LPDDR 8Gb lpddr2 256mb NT6DM32M16AD-T1 nanya lpddr2 spec

    NT6SM16M16AG-S1

    Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64
    Text: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle


    Original     		PDF 256Mb NT6SM16M16AG NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 NT6SM16M16AG-S1 lpddr2-s2 NT6SM16M16AG-S1I 128T64

    NT6DM16M

    Abstract: No abstract text available
    Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver


    Original     		PDF 512Mb NT6DM32M16AD NT6DM16M32AC -32Meg 32M16 -16Meg 16M32 NT6DM16M

    NT6TL32M

    Abstract: No abstract text available
    Text: 512Mb LPDDR2-S4 SDRAM NT6TL16M32AQ/ NT6TL32M16AQ Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS,  is transmitted/received with data, to be used in capturing data at the receiver 


    Original     		PDF 512Mb NT6TL16M32AQ/ NT6TL32M16AQ NT6TL32M

    SMD MARKING CODE sdp

    Abstract: No abstract text available
    Text: 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, 128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4, MT42L384M32D3 Features Options • Ultra low-voltage core and I/O power supplies – VDD2 = 1.14–1.30V


    Original     		PDF MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4, MT42L384M32D3 09005aef84427aab SMD MARKING CODE sdp

    Untitled

    Abstract: No abstract text available
    Text: 4Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Features Automotive Mobile LPDDR2 SDRAM MT42L256M16D1, 128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 Features Options • VDD2: 1.2V • Configuration – 32 Meg x 16 x 8 banks x 1 die


    Original     		PDF MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4 134-ball 168-ball 09005aef84fe5e04

    Untitled

    Abstract: No abstract text available
    Text: 2Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive Low-Power LPDDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks MT46H64M32LF – 16 Meg x 32 x 4 Banks 128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 16 Meg x 32 x 4 Banks x 4 Features Options


    Original     		PDF MT46H128M16LF MT46H64M32LF MT46H128M32L2 MT46H256M32L4 09005aef8541eee0