145PIN Search Results

PGA145

Abstract: PGA145-C-S15U-2 PGA weight
Contextual Info: 145S8 Metal seal 145pin PGA JEDEC Code – 4.35MAX 35.56±0.3 2.54TYP 3.3±0.3 φ1.27TYP 39.0±0.4 φ0.46±0.05 39.0±0.4 Weight g R P N M L K J H G F E D C B A 35.56±0.3 2.54TYP EIAJ Package Code PGA145-C-S15U-2.54 15 14 13 12 11 10 9 8 7 INDEX AREA 6 5 4

"network interface controller"

Contextual Info: Mixed-Signal Products UT30IBDAQ-16 16-Channel Sensor Data Acquisition Device with IntelliBusTM Network Interface Data Sheet June 2011 OVERVIEW FEATURES  16 Differential Sensor Input Channels  External Temperature Sensor Input  On-Chip Temperature Sensor

SPVU019

Abstract: LAD4-LAD31
Contextual Info: SMJ34020A GRAPHICS SYSTEM PROCESSOR SGUS011D - APRIL 1991 - REVISED SEPTEMBER 2004 D D D D D D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R 132-PIN QUAD FLATPACK TOP VIEW 100 D 145-PIN GRID ARRAY PACKAGE (TOP VIEW) 1 99 33 67 66

R5F5631

Abstract: R5F563NBDDFP A083H RX631 100-6 p86 A161H ir127 capacitor PMR 202 DM IPR200 c04f
Contextual Info: Features RX63N Group, RX631 Group Renesas MCUs R01DS0098EJ0100 Rev.1.00 Jun 13, 2012 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, Ethernet MAC, full-speed USB 2.0 host/function/OTG interface, various communications interfaces including CAN, 10- & 12-bit A/D

MH64D72KLH-10

Abstract: MH64D72KLH-75
Contextual Info: Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH64D72KLH-75,-10 4,831,838,208-BIT 67,108,864-WORD BY 72-BIT Double Data Rate Synchronous DRAM Module DESCRIPTION The MH64D72KLH is 67108864 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

kt 84l

Contextual Info: CY7C385P CY7C386P » r CYPR ESS UltraLogic Very High Speed 4K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns

Contextual Info: Revision: Thursday, September 24,1992 MUR 23 1993 PRELIMINARY CYPRESS s7-W '" SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: Prelim inary Inform ation This docum ent contains inform ation on a product under developm ent. The param etric inform ation are target param eters and aie subject to change. D istinguishing Features 200, 170 M H z O peration 8:1 M ultiplexed Pixel Ports 256 x 24 C olor Palette RAM

Contextual Info: Features Datasheet RX64M Group Renesas MCUs R01DS0173EJ0100 Rev.1.00 Jul 31, 2014 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface optional , quad SPI, and CAN, 12-bit A/D

Contextual Info: User’s Manual 32 Cover RX630 Group User’s Manual: Hardware RENESAS 32-Bit MCU RX Family / RX600 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

LGA144

Abstract: XORB LGA-144 4435* mos A18E SR 2370R ic 555 block diagram 1041 p26 HD64F2378RVFQ marking 1052
Contextual Info: REJ09B0109-0600 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2378, H8S/2378R Group Hardware Manual

Contextual Info: VMEbus Interface Controller with D64 Functionality • See the VMEbus Interface H andbook for more informa­ tion Featu res • An enhanced VIC068A Functional Description — 64-bit MBLT operation — Higher transfer rate • Complete VMEbus interface controller and arbiter

Contextual Info: SMJ34020A GRAPHICS SYSTEM PROCESSOR SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004 D D D D D D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R 132-PIN QUAD FLATPACK TOP VIEW 100 D 145-PIN GRID ARRAY PACKAGE ( TOP VIEW ) 1 99 33

t1n1

Contextual Info: MC68340UM/AD Rev. 1 INTEGRATED PROCESSOR WITH DMA USER’S MANUAL f ò M O T O R O L A TABLE OF CONTENTS Paragraph Num ber T itle Page Num ber Section 1 Device Overview 1.1 1.1.1 1.1.2 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6

VIC068A-BC

Abstract: VIC068A-GC VIC068 CY7C964 LD31 VIC068A VMEbus Interface Handbook vic068a-ac
Contextual Info: VIC068A VMEbus Interface Controller Features — Seven local interrupt lines • Complete VMEbus interface controller and arbiter — 58 internal registers provide configuration control and status of VMEbus and local operations — Drives arbitration, interrupt, address modifier utility,

Cr4401

Abstract: Bt468 BT468KG200 BT468KG170 R14 P1F sxxxx
Contextual Info: Preliminary Information This docum ent contains inform ation on a product under developm ent. The parametric inform ation contains target parameters and is subject to change. Bt468 Distinguishing Features 220, 200, 170 MHz Operation 8:1 Multiplexed Pixel Ports

vic068a-bc

Abstract: A07T Shared resource arbitration
Contextual Info: fax id: 5601 VIC068A VMEbus Interface Controller — Seven local interrupt lines Featu res • Complete VMEbus interface controller and arbiter — 58 internal registers provide configuration control and status of VMEbus and local operations — 8-level interrupt priority encode

MC68322FT20

Abstract: bitblt s3 RGP 30 H1
Contextual Info: MC68322 Integrated Printer Processor User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

Contextual Info: SMJ34020A GRAPHICS SYSTEM PROCESSOR SGUS011D - APRIL 1991 - REVISED SEPTEMBER 2004 D D D D D D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R 132-PIN QUAD FLATPACK TOP VIEW 100 D 145-PIN GRID ARRAY PACKAGE (TOP VIEW) 1 99 33 67 66

R5F56218BNFP

Abstract: R5F562N8BNFP R5F56218 R5F56216 r5f562 RX621 ir234 IR247 sdc 7500 ir153
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

TMS34020-32

Abstract: SPVU019 74ALS373 TMS34010 TMS34020 TMS34020-40 TMS34020A TMS34020A-40 GSP 45T 125 C00040
Contextual Info: TMS34020, TMS34020A GRAPHICS SYSTEM PROCESSORS SPVS004B — MARCH 1990 — REVISED OCTOBER 1990 145-Pln Grid Array Package • Instruction Cycle Time: — 100 ns . . . TMS34020-40 Advance Information — 100 ns . . . TMS34020A-40 (Advance Information) — 125 ns . . TMS34020-32

VAC068A

Abstract: VIC068A B144
Contextual Info: VAC068A CYPRESS SEMICONDUCTOR Features • Optional companion part to VIC068A • Implements master/slave VMEbus in­ terface in conjunction with the VIC068A • Complete VMEbus and I/O DMA ca­ pability for a 32-bit CPU • Complete local and VMEbus memory

Mitsubishi transistor C 1588

Abstract: MH64D72KLH-10 MH64D72KLH-75 dram memory module 1993
Contextual Info: Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH64D72KLH-75,-10 4,831,838,208-BIT 67,108,864-WORD BY 72-BIT Double Data Rate Synchronous DRAM Module DESCRIPTION The MH64D72KLH is 67108864 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

MH32D72KLH-10

Abstract: MH32D72KLH-75
Contextual Info: Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32D72KLH-75,-10 2,415,919,104-BIT 33,554,432-WORD BY 72-BIT Double Data Rate Synchronous DRAM Module DESCRIPTION The MH32D72KLH is 33554432 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.