16RP6A Search Results

111J

Abstract: 16A4 16RP4A 16X4 PAL16RA8
Contextual Info: 20-Pin PAL/HAIL Devices 16P8A 16RP6A 16RP4A 16RA8 P L ^ _ > ° J 20] VCC T io |T HA CELL — 11^ RA CELL — a lt RA CELL I3 ^ RA CELL » Jo o i]]o 2 — j j ] 03 Tb] o 4 14^ RA CELL — IsQT RA CELL - ] 3 ° 5 I6 ^ [ RA CELL - u 06 17 ^ RA CELL

16RP4A

Abstract: 200S PAL16RP4A PAL16RP6A PAL16RP8A 16P8A
Contextual Info: Medium 20PA Series 16P8A, 16RP8A, 16RP6A, 16RP4A Medium 20PA Series O UTPUTS C O M B IN A T O R IA L R E G IS T E R E D tpD* ns •cc <mA) 8 6 4 8 2 4 2 5 /3 0 2 5 /3 0 2 5 /3 0 2 5 /3 0 180 180 180 180 A R R A Y IN P U T S PA LI 6P8A PAL16RP8A 16RP6A

Contextual Info: Medium 2 0P A Series 16P8A, 16RP8A, 16RP6A, 16RP4A Medium 20PA Series OUTPUTS *PD* AR R AY INPUTS PAL16P8A PAL16RP8A 16RP6A PAL16RP4A COMBINATORIAL REGISTERED 8 6 4 8 2 4 16 16 16 16 •cc ns (mA) 2 5 /3 0 2 5 /3 0 2 5 /3 0 2 5 /3 0 180 180 180 180 * 2 5 n s a ctiv e low, 3 0 n s activ e high

Z6 ITT

Abstract: Z8 ITT 16L8 16RP4A PLA 16L8
Contextual Info: ¿7/ é- .V . Ô FA IR C H ILD cs| e 0? ' A Schlum berger Company 16P8A, 16RP8A, •' 16RP6A, 16RP4A " 0 ‘ Programmable Logic Array September 1986 PRELIMINARY INFORMATION M em ory & H igh Speed Logic D e s c rip tio n The FASTPLA 16P8A S eries of hig h -p e rfo rm a n ce bipolar

Contextual Info: o / é + .„ Ô FA IR C H ILD es I o c A S c h lu m b e rg e r Co m p a n y 4 16P8A, 16RP8A, 16RP6A, 16RP4A Programmable Logic Array September 1986 PRELIMINARY INFORMATION M e m o r y & H i g h S p e e d L o g ic D e s c r ip tio n C o n n e c t io n D ia g r a m

16A4* PAL

Abstract: 16RP4A 111J 16A4 16X4 16RA8
Contextual Info: 20-Pin PAL/HAIL Devices 16P8A 16RP6A 16RP4A 16RA8 P L ^ _ > ° J 20] VCC T io |T HA CELL — 11^ RA CELL — a lt RA CELL I3 ^ RA CELL » Jo o i]]o 2 — j j ] 03 Tb] o 4 14^ RA CELL — IsQT RA CELL - ] 3 ° 5 I6 ^ [ RA CELL - u 06 17 ^ RA CELL

16LB

Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - AND LOGIC - ARRAY - - n > ID E E 10L8/-2 E E E E - AND - I H > ID

16l8

Abstract: 16x4
Contextual Info: Devices 20-Pin E E- =£> = 0 Ed e =L> = t> AND = T > AND = E > LOGIC LOGIC ARRAY i > ID E - ARRAY = £ > E H > ID E =E> - =0 - - n > ID E E 10L8/-2 H > I ID ID =E> - AND = E > 3 - ARRAY ID =E> 3 E =E> 3 = T > ID "I 3 EE EErr> AND E - LOGIC = E > ARRAY E = [>

PAL16RP

Abstract: PAL16R8A PAL16RP8A PAL16RP8ACN 16RP4A PAL16P8A PAL16R8 PAL16RP6A PAL16RP8
Contextual Info: ADV MICRO P L A / P L E / A R R AY S Tb 0257526 ADV M I C R O P L A / P L E / A R R A Y S P A L I 6 R P 8 A S e r i e s 1 6 P 8 A , D E J 02S7S5L. 0 0 27 0 7 5 96D 2 70 75 D ' 1 6 R P 8 A 1 6 R P 6 A , 1 6 R P 4 A Ordering Information Features/Benefits • Programmable polarity

L1031

Abstract: V30J S8090 Stag Programmers PAL16P8A PAL16RP4A PAL16RP6A PAL16RP6ANC PAL16RP8A L8504
Contextual Info: /< * L i' JjW M National Æ /m Semiconductor January 1986 000965 Corporation T Programmable Array Logic PAL ) High Speed PAL Series 20 AP General Description The PAL family utilizes National Semiconductor’s Schottky TTL process and bipolar PROM fusible-link technology to

P5C032-35

Abstract: P5C032-30 5C032 EPROM 30 pin programmer schematic EP3201 EP320 PLA 16L8 16H8 16L2 16L8
Contextual Info: in tJ , 5C032 8-MACROCELL CMOS PLD • High-Density, Low-Power Replacement lo r SSI & MSI Devices and Bipolar PLDs ■ Programmable “Security Bit” Allows Total Protection of Proprietary Designs ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs

PAL16R8A

Contextual Info: P A L I 6 R P 8 A S e r ie s 1 6 P 8 A , 1 6 R P 8 A 1 6 R P 6 A , 1 6 R P 4 A Ordering Information Features/ Benefits • Programmable polarity PAL16RP8A C N STD • High speed at 25 ns tPD • Register preload • Power-up reset • Security fuse PROGRAMMABLE3

16x4

Abstract: 16A4 16l8 16L8-25 aml 10 series
Contextual Info: Devices 20-Pin E E- =£> = 0 Ed e =L> = t> AND = T > AND = E > LOGIC LOGIC ARRAY i > ID E - ARRAY = £ > E H > ID E =E> - =0 - - n > ID E E 10L8/-2 H > I ID ID =E> - AND = E > 3 - ARRAY ID =E> 3 E =E> 3 = T > ID "I 3 EE EErr> AND E - LOGIC = E > ARRAY E = [>

16L8A-4

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - - ID E E 10L8/-2 - AND - ARRAY - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE 16R8/B/B-2/B-4

16L8B-4

Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - - ID E E 10L8/-2 - AND - ARRAY - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3

pal20s

Abstract: PAL14H4-2 HAL16L8 HAL20S10 HAL16L8A-2 HAL20L8A PAL16R4A-2
Contextual Info: PAL -Programmable Array Logic H AL-Hard Array Logic Features/ Benefits • Reduce* SSI/MSI chip count peeler than 5 to 1 • Save* apace with SKINNYDIP® packages In addition the PAL/HAL provides these options: • Variable Input/output pin ratio • Programmable three-state outputs

Contextual Info: P A L I 6 R P 8 A S e r ie s 1 6 P 8 A , 1 6R P 8A 1 6R P 6A , 1 6R P 4A Ordering Information Featu res/ Benefits • Programmable polarity PAL16RP8A C N STD IT -PROCESSING • High speed at 25 ns tPD PROGRAMMABLE ARRAY LOGIC • Register preload • Power-up reset

intel eprom Intelligent algorithm

Abstract: programmer schematic ep320 P5C032-35 5c03235 P5C032 290155 P5C032-40 EP3201 D5C032-35
Contextual Info: i n t o l . 5C032 8-MACROCELL CMOS PLD • High-Density, Low-Power Replacement for SSI & MSI Devices and Bipolar PLDs ■ Programmable “Security Bit” Allows Total Protection of Proprietary Designs ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs

5C031

Abstract: PLA 16L8 5CO31 16L2 16L8 16R8 74HC EP310 EP310 programmable 290154
Contextual Info: 5C031 300 GATE CMOS PLD • High Density, Low Power Replacement for SSI & MSI Devices and Bipolar PLDs. ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs. ■ Eight Macroceiis with Programmable I/O Architecture. ■ tpo = 40 ns (max), 29.4 MHz Pipelined,

palasm

Abstract: HAL 16L8 MONOLITHIC MEMORIES ZHAL10H8A ZHAL10L8A ZHAL12H6A ZHAL12L6A ZHAL14H4A ZHAL14L4A ZHAL16C1A ZHAL16H2A
Contextual Info: Zero Power CMOS Hard Array Logic ZHAL 20A Series Patent Pending Features/ Benefits Ordering Information • Zero standby power • 25-ns maximum propagation delay PART NUMBER PACKAGE ARRAY OUTPUTS REG COMB • HC and HCT compatible • Space saving PLCC available

16R8A

Contextual Info: Zero Power CMOS Hard Array Logic ZHAL 20A Series Features/ Benefits Ordering Information • Zero standby power PART NUMBER • 25-ns maximum propagation delay PACKAGE ARRAY OUTPUTS COMB REG • HC and HCT compatible • Space saving PLCC available • Low power alternative for Small and Medium 20-pln PAL

Kontron MPP80S

Abstract: PAL VIHH programming pulse 436Z Stag Programmers 16RP4A PAL16P8A PAL16RP4A PAL16RP6A PAL16RP6ANC PAL16RP8A
Contextual Info: C t-9 January 1986 000965 T Programmable Array Logic PAL High Speed PAL Series 20 AP General Description The PAL family utilizes National Semiconductor's Schottkv TTL process and bipolar PROM fusible-link technology to provide user-programmable logic to replace conventional

16R8A

Abstract: 16H2A
Contextual Info: Zero Power CMOS Hard Array Logic ZHAL 20A Series Ordering Information Features/ Benefits • Zero standby power PART NUMBER • 25-rw maximum propagation delay PACKAGE ARRAY OUTPUTS COMB REG • HC and HCT compatible • Space tavlng PLCC available • Low power alternative lor Small and Medium 20-pln PAL«

PLA 16L8

Abstract: 5c031 290154 EP310C D5C031-50
Contextual Info: intei 5C031 300 GATE CMOS PLD • High Density, Low Power Replacement for SSI & MSI Devices and Bipolar PLDs. ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs. ■ Eight Macrocelis with Programmable I/O Architecture. ■ tpo = 40 ns (max), 29.4 MHz Pipelined,