1992R Search Results

Contextual Info: S O N Y C XA 1992R Preliminary RF Signal Processing Servo Amplifier Description The 1992R is a bipolar IC developed for CD player RF signal processing and servo control. This IC supports three-spot optical system pickups. Features • Automatic focus bias adjustment circuit

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

Contextual Info: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted

Video RAM

Abstract: TMS55165
Contextual Info: TMS55165 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS165B-AUGUST1992-flEVISED JANUARY 1993 DGH PACKAGEt TOP VIEW DRAM : 262 144 Words x 16 Bits SAM: 256 Words x 16 Bits Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports

44460D

Abstract: BK36C-80
Contextual Info: TM124MBK36C, TM124MBK36S1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS138B - MARCH 1992 - REVISED JUNE 199S Enhanced Page Mode Operation With CAS-Before-RAS CBR , RAS-Only, and Hidden Refresh Presence Detect Performance Ranges:

27A6

Contextual Info: TMS28F210 1048576-BIT FLASH MEMORY I SMJS210B - DECEMBER 1892 - REVISED JUNE 1995 N PACKAGE TOP VIE W Pin Compatible With Existing 1-Megabit EPROMs All Inputs/Outputs TTL Compatible Vcc Tolerance ±10% Maximum Access/Minimum Cycle Time ’28F210-10 100 ns

Contextual Info: CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS _ SCAS335A-DECEMBER 1992-R E V IS E D NOVEMBER 1995 D PACKAGE TOP VIEW Low Output Skew for Clock-Distribution and Clock-Generatlon Applications

SPW 12w

Abstract: TMS380c16 RRU 32
Contextual Info: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options

D2B4

Abstract: H1B13
Contextual Info: SN54ABT32543, SN74ABT32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230B - JUNE 1992 - REVISED JULY 1994 • Members of the Texas Instruments Wldebus+ Family • State-of-the-Art EPIC-llB™ BICMOS Design Significantly Reduces Power Dissipation

Contextual Info: SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS _ SCBS160C- DECEMBER 1992 - REVISED MAY 1997 Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-llB™ BiCMOS Design Significantly Reduces Power Dissipation

Contextual Info: TMS55160 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS160B-AUGUST1992-REVISED JANUARY 1993 * * * * * DGH PACKAGEt DRAM : 262144 Words x 16 Bits SAM: 256 Words x 16 Bits TOP VIEW Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and

QS3384

Abstract: QS3L384 SN74CBT3384A
Contextual Info: SN74CBT3384A 10-BIT BUS SWITCH S C D S 004F- NOVEMBER 1992 - REVISED AUGUST 1996 • Functionally Equivalent to QS3384 and QS3L384 DB, DW, OR PW PACKAGE TOP VIEW • 5-i2 Switch Connection Between Two Ports 10 E [ 1 1B1 [ 2 • TTL-Compatible Input and Output Levels

62d18

Abstract: fifo ttl B129 B249 SN74ACT2226 SN74ACT2228
Contextual Info: SN74ACT2226, SN74ACT2228 DUAL 6 4 x 1 AND DUAL 256x1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219A - JUNE 1992-R E V IS E D AUGUST 1993 Dual Independent FIFOs Organized as: - 64 Words by 1 Bit Each - SN74ACT2226 - 256 Words by 1 Bit Each - SN74ACT2228 Free-Running Read and Write Clocks Can

TLV2217-33

Abstract: TLV2217-33KC TLV2217-33N TLV2217-33PWLE TLV2217-33Y 106C CAPACITOR
Contextual Info: TLV2217-33, TLV2217-33Y LOW-DROPOUT 3.3-V FIXED VOLTAGE REGULATORS SLVS067A- MARCH 1992 - REVISED NOVEMBER 1992 Fixed 3.3-V Output +1% Maximum Output Voltage Tolerance at T j = 25°C 5 0 0 -mV Maximum Dropout Voltage at 500 mA NPACKAGE {TOP VIEW u ] NC ] OUTPUT

74ACT11657

Contextual Info: _ 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS AUGUST 1992-R EVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout P A R IT Y [ 1 Center-Pin V c c and GND Pin

QS3244

Abstract: SN74CBT3244
Contextual Info: SN74CBT3244 OCTAL BUS SWITCH SCDS001E-N O VEM B ER 1992-R E V IS E D JUNE 1996 • Functionally Equivalent to QS3244 • Standard ’244-Type Pinout DB, DW, OR PW PACKAGE TOP VIEW • 5-& Switch Connection Between Two Ports • TTL-Compatible Control Input Levels

LVT16374

Contextual Info: SN54LVT16374, SN74LVT16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS145B- MAY 1 9 9 2 - REVISED FEBRUARY 1994 SN54LVT16374 . . . WD PACKAGE SN74LVT16374. . . DGG OR DL PACKAGE {TOP VIEW State-of-the-Art Advanced BiCMOS Technology ABT) Design for 3.3-V

SN74ABT3611

Abstract: mdv 434
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SC B S 127C - JULY 1992 - RE V IS E D A P R IL 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Empty Flag EF and Almost-Empty Flag (AE) Synchronized by CLKB 64 x 36 Clocked FIFO Buffering Data From

I3B2

Abstract: J10B1 SN74CBT16212 8B221 10A1 10B1 10B2 11A2 12A2 12B1
Contextual Info: SN74CBT16212 24-BIT BUS-EXCHANGE SWITCH SC DS007A- NOVEMBER 1 9 9 2 - REVISED MARCH 1994 • 5-i2 Switch Connection Between Two Ports • TTL-Compatible Input and Output Levels • Packaged in Plastic 300-mil Shrink Small-Outline DL and Thin Shrink Small-Outline (DGG) Packages

D4042

Abstract: 74HC241 75LBC176 SN75LBC976
Contextual Info: SN75LBC976 9-CHANNEL DIFFERENTIAL TRANSCEIVER SLLS133B - D4042, AUGUST 1992 - REVISED FEBRUARY 1993 9 Differential Channels for the Data and Control Paths of the Differential Small Computer Systems Interface SCSI and Intelligent Peripheral Interface (IPI-2)

Contextual Info: SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS131-AUGUST 1992-REVISED OCTOBER 1992 • SCOPE Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1 A CLAMP and HIGHZ - Parallel Signature Analysis at Inputs With

MAKING CODE 1H sod

Contextual Info: TMS34094 ISA BUS INTERFACE S PV S 006A - FEBRUARY 1992 - REVISED JUNE 1992 • Simplifies Design of High-Performance ISA PC Graphics Systems • Single-Integrated Circuit Interfaces TMS34020 to ISA Bus • Conforms to ISA Portions of the EISA Rev. 3.11 Specifications

Contextual Info: SN54ABT18245A, SN74ABT18245A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS SCBS110G-AUGUST 1992-REVISED DECEMBER 1996 M e m b e r s of the Texas I n s t r u m e nt s S C O P E F a mi l y of Testabil ity P r o d u c t s SN54ABT1 8245A . . . WD PACKAGE

Contextual Info: TLC2274, TLC2274A, TLC2274Y Advanced LinCMOS RAIL-TO-RAIL QUAD OPERATIONAL AMPLIFIERS SLOS106C - MARCH 1992 - REVISED AUGUST 1994 • • • • Output Swing Includes Both Supply Ralls Low Noise. . . 9 nV/VHz Typ at f = 1 kHz Low Input Bias Current. . . 1 pA Typ