2.048 MHZ Search Results

Contextual Info: intJ. 2916/2917 HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER 2916 ft-Law, 2.048 MHz Master Clock Fixed Timing Mode for Standard 32-Channel Systems: 2.048 MHz Master Clock 2917 A-Law, 2.048 MHz Master Clock New 16-Pin Package for Higher Linecard Density Low Power HMOS-E Technology

Contextual Info: Farnell Order Code: 1640989 FOX MODEL: FXO-HC736R-2.048 FOX Part Number: 768-2.048-56 HCMOS, CERAMIC, SMD, OSCILLATOR A. Specifications Parameters Frequency Frequency Stability 1 Temperature Range Operating TOPR Storage (TSTG) Supply Voltage (VDD) (IDD)

T7517

Contextual Info: T7516 and T7517 PCM Codecs With Filters Features T7516: /i-law companding, 2.048 MHz master clock T7517: A-law companding, 2.048 MHz master clock Direct replacement for the industry-standard 2916 and 2917 devices Low-power, latchup-free CMOS technology — 65 mW typical operating power dissipation

ZL30112

Abstract: zl30112lde1 3 phase automatic change over switch circuit diagram "network interface cards"
Contextual Info: ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2007 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail

ZLAN-68

Abstract: "network interface cards"
Contextual Info: ZL30112 SLIC/CODEC DPLL Data Sheet Features May 2009 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail

QPSK demodulator delay

Abstract: RVAA
Contextual Info: Mfa. MICROWAVE BROADCAST MODEM ML 22000 DATA ABOVE VIDEO MODULATOR/DEMODULATOR 2.048 MBIT/S DESCRIPTION The M L 22000-TVAA modulator unit accepts a video signal of up to 5.5 MHz bandw idth and a 2.048 Mbps data stream on separate inputs. The digital signal is processed and used to QPSK

Contextual Info: Farnell Order Code: 1641023 FOX MODEL: FXO-HC536R-2.048 FOX Part Number: 767-2.048-13 HCMOS, CERAMIC, SMD, OSCILLATOR Specifications Parameters Frequency Frequency Stability 1 Temperature Range Operating TOPR Storage (TSTG) Supply Voltage (VDD) Input Current

Contextual Info: ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2009 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail

HIGHWAY 08 20 PIN IC PIN DIAGRAM

Contextual Info: ^ IL O ÌM O IM « 2916 AND 2917 16-PIN SINGLE CHIP PCM CODEC AND FILTER • 2916/u-Law, 2.048 MHz Master Clock ■ 2917 A-Law, 2.048 MHz Master Clock ■ New 16-Pin Package for Higher Linecard Density ■ Fully Differential Architecture Enhances Noise Immunity

MS2 IR

Contextual Info: ZL30462 Compact Timing Module Data Sheet Features January 2005 • Complete timing solution in a small outline package • 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference frequencies • 8 kHz frame pulse , 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz and two 155.52 MHz

"network interface cards"

Contextual Info: ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2007 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail

Contextual Info: A FLESSE Y W Semiconductors, 2 MBIT PCM SIGNALLING CIRCUIT M J 1440 HDB3 ENCODER/DECODER The 2.048 MBit PCM Signalling Circuits comprise a group of circuits which will perform the common signalling and error detection functions for a 2.048 MBit PCM trans­

Stanford Telecom

Contextual Info: STEL-2048 Data Sheet STEL-2048/CM 2.048 Mbps Viterbi Decoder STANFORD TELECOM* 6505242 DQDEbfib TSE • FEATURES FUNCTIONAL DESCRIPTION H 2.048 Mbps Maximum Operating Rate Convolutional encoding and Viterbi decoding are used to provide forward error correction FEC which improves

ZL30111

Abstract: ZL30111QDG ZL30111QDG1
Contextual Info: ZL30111 POTS Line Card PLL Data Sheet Features January 2007 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides a range of clock outputs: 2.048 MHz, 4.096 MHz and 8.192 MHz • Provides 2 styles of 8 kHz framing pulses • Automatic entry and exit from freerun mode on

sinusoidal

Abstract: POWER SUPPLY 2916 fxs interface integrated circuit
Contextual Info: in t j, 2916/2917 HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER 2916 /x-Law, 2.048 MHz Master Clock 2917 A-Law, 2.048 MHz Master Clock New 16-Pin Package for Higher Linecard Density AT&T D3/D4 and CCITT Compatible Variable Timing Mode for Flexible Digital Interface: Supports Data Rates

MJ1444

Abstract: g732 MJ1445 TS16
Contextual Info: MJ1444 2 MBIT PCM SIGNALLING CIRCUIT MJ1444 PCM SYNCHRONISING WORD GENERATOR The 2.048 Mbit PCM signalling circuits comprise a group of circuits which will perform the common signalling and error detection functions for a 2.048 Mbit 30 channel PCM transmission link operating to the appropriate CCITT

Contextual Info: T1/E1 Primary Rate Specifications Primary Rate Specifications Function DSX-1 DS-1 T1.403 Line Rate C able Length S2 (G.703) (1.431) 1.544 MHz 1.544 MHz 2.048 MHz 2.048 MHz ± 200 B/S ± 75 B/S ± 50 ppm ± 50 ppm ABAM/655 ft 3000/6000 ft 350 m 1000 m (1000 ft)

Alternate Mark Inversion

Abstract: MJ1440 HDB3 bin ENCODER DECODER E2 hdb3 HDB3 G703 PCM encoder circuit ternary HDB3 to nrz
Contextual Info: MJ1440 2 MBIT PCM SIGNALLING CIRCUIT M J 1440 HDB3 ENCODER/DECODER The 2.048 MBit PCM Signalling Circuits comprise a group of circuits which will perform the common signalling and error detection functions for a 2.048 MBit PCM trans­ mission link operating to the appropriate CCITT recomm­

29C16

Abstract: 29c17 TF DKL
Contextual Info: A G M Ä M ! O M IP Û fô G M T O N ] in te T 29C16 AND 29C17 16 PIN CHMOS SINGLE CHIP PCM CODEC AND FILTER • 29C16 ju-Law, 2.048 MHz Master Clock ■ 29C17 A-Law, 2.048 MHz Master Clock 3 Low-Power Modes — 3.5 mW Typical Power Down — 3.5 mW Typical Standby

MT90863

Abstract: MT90863AG MT90863AL MT90863AL1 IC1 4047
Contextual Info: MT90863 3 V Rate Conversion Digital Switch Data Sheet Features May 2006 • 2,048 x 512 and 512 x 512 switching among backplane and local streams • Rate conversion between 2.048, 4.096 and 8.192 Mb/s • Optional sub-rate switch configuration for 2.048 Mb/s streams

Contextual Info: W R î- ' t^ 2 Data Sheet March 1992 , â A T s r Microelectronics T7288 CEPT1 Line Interface Features Description • Fully Integrated 2.048 M bits/s line interface The T7288 CEPT1 Line Interface is an integrated circuit that provides a 2.048 M bits/s line interface to

MJ1445

Abstract: g732 MJ1444 Q732
Contextual Info: MJ1445 A P LE S S E Y W S em ico n d u cto rs PCM SYNCHRONISING WORD RECEIVER MJ1445 2 MBIT PCM SIGNALLING CIRCUIT The 2.048 Mbit PCM signalling circuits comprise a group of circuits which will perform the common signalling and error detection functions for a 2.048 MBit 30 channel

HIGHWAY 08

Abstract: ami circuit diagram Digital Alarm Clock on ttl MJ1446 TS16 ami pcm TP170 Digital Alarm Clock by ttl Digital Alarm Clock 40 pin pcm ami
Contextual Info: MJ1446 APLESSEY W S em ico n d u cto rs — —i 2 MBIT PCM SIGNALLING CIRCUIT MJ1446 TIME SLOT 16 RECEIVER AND TRANSMITTER The 2.048 Mbit PCM signalling circuits comprise a group of circuits which will perform the common signalling and error detection functions for a 2.048 Mbit 30 channel

HDB3

Abstract: HDB3 bin ENCODER DECODER HDB3 CODING DECODING G703 MJ1440
Contextual Info: A PLESSE Y ’w S e m ic o n d u c to rs , 2 MBIT PCM SIGNALLING CIRCUIT MJ 1440 HDB3 ENCODER/DECODER The 2.048 M B it PCM S ignalling C ircuits com prise a group o f circ u its w hich w ill perform the com m on signalling and error de tection functions fo r a 2.048 M B it PCM trans­