231466 Search Results

Contextual Info: Extract from the online catalog CABLE-50/4FLK14/ 3,0M/YUC Order No.: 2314668 Assembled round cable with a 50-pos. molded socket strip and four 14-pos. socket strips, for splitting 32 channels into 4 x 8 channels,

ADV551

Contextual Info: Extract from the online catalog CABLE-50/4FLK14/ 3,0M/YUC Order No.: 2314668 Assembled round cable with a 50-pos. molded socket strip and four 14-pos. socket strips, for splitting 32 channels into 4 x 8 channels,

231466

Abstract: AP 67 interfacing of 8237 with 8085 interfacing of 8237 with 8086 8237 interface with 8086 Peripheral block diagram 8284A clock generator driver 8086 8237A-5 8237A transfer modes TCYb100 8085 microprocessor
Contextual Info: 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A-5 Y Enable Disable Control of Individual DMA Requests Y Directly Expandable to Any Number of Channels Y Four Independent DMA Channels Y Y Independent Autoinitialization of All Channels End of Process Input for Terminating

AP 67

Abstract: 8237 interface with 8086 Peripheral block diagram 8237A
Contextual Info: intei 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A, 8237A-4, 8237A-5 • Enable/Disable Control of Individual DMA Requests ■ Directly Expandable to Any Number of Channels ■ Four Independent DMA Channels ■ End of Process Input for Terminating

Intel 8237A

Abstract: intel 8237A DMA Controller 231369 8237A-5
Contextual Info: Intel 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A-5 • Enable/Disable Control of Individual DMA Requests ■ Four Independent DMA Channels ■ Independent Autoinitialization of All Channels ■ Memory-to-Memory Transfers ■ Memory Block Initialization

8080 data bus timing diagram

Abstract: 8080, 8224, and 8228 8228 DI 8238 intel 8228 bus controller intel 8238 intel 8228 MCS-80 H10A 8080
Contextual Info: inter 8228/8238 SYSTEM CONTROLLER AND BUS DRIVER FOR 8080A CPU User Selected Single Level Interrupt Vector RST 7 8238 Has Advanced IOW/MEMW for Large System Timing Control Available in EXPRESS — Standard Temperature Range Available in 28-Lead Cerdip and Plastic

intel 8237A DMA Controller

Abstract: 231369 8237A-5 8237A transfer modes order 231369
Contextual Info: inU. 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A-5 • ■ ■ ■ ■ ■ ■ ■ Enable/Disable Control of Individual DMA Requests Four Independent DMA Channels Independent Autoinitialization of All Channels Memory-to-Memory Transfers Memory Block Initialization

MIL-C-39012 SMA SPEC

Abstract: thermofit
Contextual Info: K SERIES K SERIES K RF COAXIAL CONNECTORS Series K millimeter wave style RF connector is developed based on series SMA. It can crossing-over with series SMA, used in air interface. Series K connector has many advantages, such as small size, light weight, high frequency and reliable connection etc.

DRE01

Abstract: 8237A-5 intel 8237A DMA Controller
Contextual Info: intJ 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A-5 • Enable/Disable Control of Individual DMA Requests ■ Directly Expandable to Any Number of Channels ■ Four Independent DMA Channels ■ End of Process Input for Terminating Transfers ■ Independent Autoinitialization of All

Intel 8237A

Abstract: interfacing of 8237 with 8086 Intel 8237 dma controller block diagram MC01 8237A DMA interface 8237 WITH 8088 interfacing of 8237 with 8085 8085AH 8085AH-2 82C84A
Contextual Info: in tj, 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A, 8237A-4, 8237A-5 • E n a b le /D is a b le C o n tro l o f Ind ividu al D M A R e q u es ts ■ D ire c tly E xp a n d ab le to A n y N u m b er o f C h an n els ■ F ou r In d e p e n d e n t D M A C h an n els

Intel 8237A

Abstract: interfacing of 8237 with 8086 DMA interface 8237 WITH 8088 8237 interface with 8086 Peripheral block diagram intel 8282 latch interfacing of 8237 with 8085 AP-67 8086 Intel 8237 8085AH 8085AH-2
Contextual Info: in te i 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A, 8237A-4, 8237A-5 Enable/D isable Control of Individual DMA Requests Directly Expandable to Any Num ber of Channels Four Independent DMA Channels End o f Process Input fo r Term inating Transfers