25 Q 80 Search Results

Contextual Info: □ IXYS VDSS HiPerFET Power MOSFETs 27N80 IXFK 25N80 IXFN 27N80 IXFN 25N80 ix f k N-Channel Enhancement Mode AvalancheRated, High dv/dt, Lowtrr 800 800 800 800 V V V V D ^D25 27 25 27 25 A A A A D S o n 0.30 0.35 0.30 0.35 Q Q Q Q TO -264A A (IX FK )

LTC5584

Abstract: LTC5585 LT5516 DN1027 LT5575
Contextual Info: Ultra-Wideband, High Linearity I/Q Demodulators 120 DC Offset IIP2 Optimization Cancellation I 700MHz to 3GHz 100 IIP2 dBm LTC5585 0° 25.7dBm IIP3 at 1.9GHz I, –40°C I, 25°C I, 85°C I, 105°C 110 Q, –40°C Q, 25°C Q, 85°C Q, 105°C fRF = 1950MHz

GAL programmer schematic

Abstract: gal programmer gal programming algorithm 16v8h 16V8Z-25 16v8h-10 palce16v8 programming algorithm 16V8H-5 GAL 16 v 8 D pal16r8 programming algorithm
Contextual Info: PALCE16V8 PALCE16V8Z COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25 COM’L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all 20-pin PAL devices

palce16v8 programming algorithm

Abstract: 16v8z PAL 16V8Q 16V8H-15 16V8Z-25 automatic change over switch circuit diagram pal16r8 programming algorithm GAL programmer schematic 16V8H-5 16V8H-10
Contextual Info: PALCE16V8 PALCE16V8Z COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/25, Q-20/25 COM’L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all 20-pin PAL devices

palce16v8 programming algorithm

Abstract: 16V8Q PAL16L8 programming algorithm 16V8H-15 PAL 16V8Q 16V8H-10 16V8H-5 16v8h 16v8h-7 16V8Z-25
Contextual Info: PALCE16V8 PALCE16V8Z COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/25, Q-20/25 COM’L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all 20-pin PAL devices

PH1090-700B

Abstract: Mode-S transistor
Contextual Info: Avionics Pulsed Power Transistor, 700 Watts, 12/10/01 1.03-1.09 GHz, 32 µS Pulse, 2% Duty PH1090-700B Rev. 0 Features Q Q Q Q Q Q Q Q Absolute Maximum Ratings @ 25 °C Designed for Mode-S IFF Applications NPN Silicon Microwave Power Transistor Common Base Configuration

16v8h

Abstract: 16V8Q palce16v8 programming algorithm 16v8z PAL16C1 PAL16R8 PALCE16V8 PALCE16V8Z 16V8H-10 16v8z-25
Contextual Info: PALCE16V8 PALCE16V8Z COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/25, Q-20/25 COM’L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all 20-pin PAL devices

iP2970

Abstract: palce16v8 programming guide
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 MIL: H-15/20/25 PALCE16V8 Family AdvaM "£o EE CMOS 20-Pin Universal Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • ■ ■ Pin, function and fuse-map compatible with all 20-pin GAL devices

palce16v8 programming algorithm

Abstract: AMD palce16v8 programming palce16v8 programming guide palce16v8z pal16r8 programming algorithm APL DOC SIC jmd PROGRAMMER PAL16R8 algorithm amd palce programming Guide palce16v6
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 a MIL: H-15/20/25 Advanced Micro Devices PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pin GAL devices

16V8H-15

Abstract: palce16v8 programming algorithm 16V8Q 16V8H-10 AMD palce16v8 programming 16v8h-7 PAL10H8 PAL16C1 PAL16R8 PALCE16V8
Contextual Info: FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity

20v8h

Abstract: 20V8Q
Contextual Info: COM'L: H-5/7/10/15/25, Q-15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

palce16v8 programming algorithm

Abstract: palce22v10 programming guide automatic change over switch circuit diagram PAL16L8 programming algorithm palce programming algorithm palce programming Guide GAL programming Guide PALCE erase 16V8H-10 HC CMOS family characteristics
Contextual Info: FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity

TP25N05

Abstract: TP25N
Contextual Info: £jï 25 05 25 05 SGS-THOMSON ULKgraMOeS STP N STP N FI N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR TYP E V S TP25N 05 STP25N 05FI . . . . . . . . dss 50 V 50 V RDS on Id < 0 .0 6 5 Q. < 0 .0 6 5 Q. 25 A 16 A TYPICAL R DS(on) = 0.048 Q. AVALANCHE RUGGED TECHNOLOGY

GAL20V8

Abstract: PAL20R8 PALCE20V8
Contextual Info: FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all GAL ■ ■ ■ ■ ■ ■ Peripheral Component Interconnect PCI

plji

Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25. Q-20/25 MIL: H-15/20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all GAL 20V8/AS ■ Electrically erasable CMOS technology pro­

htw 323

Abstract: plji palce programming algorithm
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25. Q-20/25 MIL: H-15/20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all GAL 20V8/AS ■ Electrically erasable CMOS technology pro­

20v8q

Abstract: 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PAL20V8 PD3024 PALCE20V8H5JC5
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

PAL20L2 programming specification

Abstract: 20v8q SL0311 20V8H-5 PALCE20V8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

20V8H-15

Abstract: Pal programming 20V8H-5 20v8h 20V8H-10 20V8 PAL20R8 PALCE20V8 GAL20V8 PAL20V8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

AMD marking CODE

Abstract: 20V8H-15 TEA 2161 AMD datecode marking CODE GAL20V8 PAL20R8 PALCE20V8 PALCE20V8H-25 AMD TOP-SIDE MARKING
Contextual Info: FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 Advanced Micro Devices PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all GAL ■ ■ ■ ■ ■ ■ Peripheral Component Interconnect PCI

palce16v8 programming algorithm

Abstract: 16V8Q 16V8H-15 Jc 16V8H-15 16v8h PAL16L8 programming algorithm AMD palce16v8 programming gal programming algorithm gal programming timing chart SL1110
Contextual Info: FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity ■ Electrically erasable CMOS technology

ce20V8

Abstract: PALCE20V8H5JC5 GAL20V8 PAL20R8 PALCE20V8 AMD TOP-SIDE MARKING
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic z\ Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all GAL 20V8/As ■ Electrically erasable CMOS technology pro­

15015 3524

Abstract: D-35 RS-100 RS-150 RS-35 RS-50 RS-75 1.0A
Contextual Info: G3 Series 25~150W High Reliability Miniature 1~4 Output Features RS-150 RD/ID/T/Q-125 RS-100 RD/ID/T/Q-85 RS-75 RD/ID/T/Q-65 RS-50 RD/ID/T/Q-50 R S -35 R D-35 R S -25 General Specification Please refer to www.meanwell.com for detail spec. MODEL No. RS-35

20V8Q

Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability