PD3024 Search Results

PD3024

Abstract: la 1240 CFM024
Contextual Info: PACKAGE OUTLINES* PD3024 1.240 1.280 24 13 ID 1 12 i .240 290 -4 ♦ •*— .006 MIN. SEA TIN G P LA N E ■140 CD3024 1.235 1.280 .096 MAX. 290 *For reference only. 111 PACKAGE OUTLINES Cont'd. SO 024 .6141 ' .0926 — J i r u JL l l l : . : . : . : - L

gal programming algorithm

Abstract: PALCE29M16 PALCE29M16H PALCE29M16H-25 PD3024
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-25 Lattice Semiconductor PALCE29M16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • High-performance semicustom logic ■ Register/Latch Preload permits full logic replacement; Electrically Erasable EE

20V8Q

Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

sfe 5,5 ma

Abstract: CD3024 PD3024
Contextual Info: >rJ , J Am 29C?33/834 CMOS Parity Bus Transceivers PRELIMINARY > > 3 3 DISTINCTIVE CHARACTERISTICS • • • Low-power CMOS - ICC Static = 80 //A High-speed bidirectional bus transceiver for processor organized devices Error flag with open-collector output

CD3024

Abstract: PD3024 AM2S
Contextual Info: Am 29833A/834A - Am 29853A/854A Parity Bus Transceivers PRELIMINARY DISTINCTIVE CHARACTERISTICS High-speed bidirectional bus transceiver for processor organized devices Error flag with open-collector output Generates odd parity for all-zero protection Buffered direction three-state control

Am2963

Contextual Info: Am29833A/Am29853A/Am29855A Parity Bus Transceivers VSS86ZUJV/V8S86ZUIV/VSC86ZUIV DISTINCTIVE CHARACTERISTICS • High-speed bidirectional bus transceivers for processor organized devices - T-R delay = 6 ns typical - Rj-Parity delay = 9 ns typical • Error flag with open-collector output

PAL32VX10

Contextual Info: COM’L Advanced Micro Devices PAL32VX10/A 24-Pin Versatile with XOR Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Increased logic power ■ Global register asynchronous/synchronous preset/reset ■ Automatic register preset on power up ■ Preloadable output registers for testability

pal20ra10 mmi

Abstract: PAL20RA10
Contextual Info: COM’L : -20/std MIL: std Advanced Micro Devices PAL20RA10/-20 24-pin Asynchronous TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 20 ns maximum propagation delay and 30 MHz fMAx ■ Individually programmable asynchronous clock, preset, reset, and enable

amd 20l10

Abstract: CED registers
Contextual Info: 24-Pin Enhanced Am PAL20RP10 Fam ily 24-Pin IMOX Programmable Array Logic PAL Elements D is tin c tiv e C h a ra c te ris tic s • • • • • • • PRELOAD feature permits full logical verification Reliability assured through more than 70 billion fuse

Contextual Info: AmPALC29M Al 6 24-Pin E2-Based CMOS Programmable Array Logic ADVANCE INFORMATION Distinctive Characteristics • • • • • High-performance semi-custom logic replacement; Electrically Erasable E2 technology allows repro­ grammability 16 bidirectional user-programmable I/O logic macro­

Contextual Info: Am27S35/Am27S37 8,192-Bit 1024x8 Bipolar Registered PROM with Programmable INITIALIZE Input Versatile programmable asynchronous or synchronous enable for simplified word expansion Buffered common INITIALIZE input either asynchronous (Am27S35) or synchronous (Am27S37)

Contextual Info: COM’L PLS167-33, PLSCE167H-33 PLS168-33, PLSCE168H-33 Advanced Micro Devices 24-Pin TTL/CMOS Programmable Logic Sequencers DISTINCTIVE CHARACTERISTICS • ■ Field-programmable replacement for sequential control logic User-programmable pin for asynchronous

Contextual Info: Am29C827/Am29C828 Am29C927/Am29C928 Am29C827/Am29C828 Am29C927/Am29C928 High-Performance CMOS Bus Buffers DISTINCTIVE CHARACTERISTICS • • • High-speed CMOS buffers and inverters - D-Y delay = 7 ns typical Low standby power JEDEC FCT-compatible specs

Contextual Info: COM’L :-7/10/15 a MIL: -12/20 Advanced Micro Devices PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns propagation delay and 91 MHz fMAx external ■ 10 Macrocells programmable as registered or

Contextual Info: FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 PALCE20RA10 Family AduaM nlccero 24-Pin Asynchronous EE CMOS Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • ■ Low pow er at 100 m A Icc ■ TTL-level register preload for testability A s fast as 7.5 ns m axim um propagation delay

Am29C82

Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •

AMPAL22V10

Contextual Info: A m P A L 2 2 V 1 0-1 5 24-Pin IM O X III7“ Program m able Array Logic P R E L IM IN A R Y Distinctive Characteristics • • • • • • • • • 15-ns perform ance Increased logic pow er — up to 22 inputs and 10 outputs Increased product term s — average 12 per output

27S181

Abstract: Am27S181/27S181
Contextual Info: A m a 2 7 S 1 8 1 /2 7 S 1 8 1 A A m 2 7 S 2 8 1 Advanced Micro Devices /2 7 S 2 8 1 A 8,192-Bit 1024x8 Bipolar PROM DISTINCTIVE CHARACTERISTICS • • Fast access time allows high system speed 50% power savings on deselected parts — enhances reliability through total system heat reduction

am7992bdc

Abstract: manchester decoder
Contextual Info: Am7992B Advanced Micro Devices Serial Interface Adapter SIA DISTINCTIVE CH ARACTERISTICS • Crystal/TTL oscillator controlled Manchester Encoder input signal conditioning rejects transient noise - Transients < 10 ns for collision detector inputs - Transients < 20 ns for carrier detector inputs

ecl pal 16 macrocells

Abstract: HD b3c
Contextual Info: AmPAL*10H20EG8/AmPAL10020EG8 IMOX-III ECL Programmable Array Logic PRELIMINARY Asynchronous-RESET and PRESET capability Power-up RESET capability PRELOAD for improved testability Special designed-ln test features for full AC and DC testing Platinum-silicide fuses ensure high programming yield,

htw 323

Abstract: plji palce programming algorithm
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25. Q-20/25 MIL: H-15/20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all GAL 20V8/AS ■ Electrically erasable CMOS technology pro­

29c833

Abstract: 29C933 amd 955
Contextual Info: Am29C833/Am29C853/Am29C855 Am29C933/Am29C953/Am29C955 Am29C833/Am29C853/Am29C855 Am29C933/Am29C953/Am29C955 High-Performance CMOS Parity Bus Transceivers DISTINCTIVE CHARACTERISTICS • • • • High-speed CMOS bidirectional bustransceivers - T-R delay = 6 ns typical

UE 40 F 6470

Abstract: pid u 13t
Contextual Info: OY i Am99C16 4 /Am99CL164 Am99C16 5 /Am99CL165 16,384x4 Static R /W Random-Access Memory PRELIMINARY DISTINCTIVE CHARACTERISTICS F ast a ccess tim e - 3 5 /4 5 /5 5 /7 0 ns maxim um 16K x 4 organization O utput Enable ÜE control to a lleviate bus-contention

slim power sata pinout

Abstract: Am27S85
Contextual Info: Am27S85/27S85A 16,384-Bit 4096x4 Registered PROM with SSR Diagnostics Capability Micro Devices DISTINCTIVE CHARACTERISTICS • • • On-chip diagnostic shift register for serial observability and controllability of the output register User-programmable for Asynchronous Enable, Synchro­