256KX16 LCAS Search Results

256kx16 ucas zip

Contextual Info: Technical Information OKI Semiconductor MSM5416256/MSM54V16256 {Standard-version _ Lowvoltago vflrsionor V-voremn)_ 262,144 Words x 16 Bits GRAPHICS BURST ACCESS MEMORY GENERAL DESCRIPTION The MSM5416256 is a high speed 256KX16 configuration burst access memory for high performance

IS41C16256C-35TLI

Abstract: IS41C16256C
Contextual Info: IS41C16256C IS41LV16256C ADVANCED INFORMATION APRIL 2010 256Kx16 4Mb DRAM WITH EDO PAGE MODE FEATURES DESCRIPTION • TTL compatible inputs and outputs • Refresh Interval: 512 cycles/8 ms • Refresh Mode : RAS-Only, CAS-before-RAS CBR , and Hidden • JEDEC standard pinout

IS41C16257C

Contextual Info: IS41C16257C IS41LV16257C 256Kx16 4Mb DRAM WITH FAST PAGE MODE JANUARY 2013 FEATURES DESCRIPTION •฀ TTL฀compatible฀inputs฀and฀outputs;฀tri-state฀I/O •฀ Refresh฀Interval:฀512฀cycles/8฀ms •฀ Refresh฀Mode:฀RAS-Only,฀CAS-before-RAS฀ CBR ,฀

IS41LV16257C

Abstract: iS41C16257C
Contextual Info: IS41C16257C IS41LV16257C 256Kx16 4Mb DRAM WITH FAST PAGE MODE JANUARY 2013 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tri-state I/O • Refresh Interval: 512 cycles/8 ms • Refresh Mode: RAS-Only, CAS-before-RAS CBR , and Hidden • JEDEC standard pinout

IS41LV16256C

Abstract: IS41C16256C
Contextual Info: IS41C16256C IS41LV16256C 256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tri-state I/O • Refresh Interval: 512 cycles/8 ms • Refresh Mode : RAS-Only, CAS-before-RAS CBR , and Hidden • JEDEC standard pinout

HY514264

Abstract: HY514264B DSA0015545 256Kx16 lcas
Contextual Info: HY514264B 256Kx16, Extended Data Out mode DESCRIPTION This family is a 4M bit dynamic RAM organized 262,144 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time 50, 60

HY514260B

Abstract: hy514260bjc HY514260
Contextual Info: HY514260B 256Kx16, CMOS DRAM with /2CAS DESCRIPTION This family is a 4M bit dynamic RAM organized 262,144 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time 50, 60

IS41C16257C

Abstract: IS41LV16257C-35KL IS41LV16257C IS41LV16257C-35KLI
Contextual Info: IS41C16257C IS41LV16257C 256Kx16 4Mb DRAM WITH FAST PAGE MODE FEATURES • • • • • • • • • Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 512 cycles/8 ms Refresh Mode: RAS-Only, CAS-before-RAS CBR , and Hidden

HY514264

Contextual Info: •HYUNDAI HY514264B 256Kx16, Extended Data Out mode DESCRIPTION This family is a 4M bit dynamic RAM organized 262,144 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time 50, 60

Contextual Info: •HYUNDAI HY514260B 256KX16, CMOS DRAM w ith /2CAS DESCRIPTION This family is a 4M bit dynamic RAM organized 262,144 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time 50, 60

Contextual Info: IC41C16257/IC41C16257S IC41LV16257/IC41LV16257S Document Title 256Kx16 bit Dynamic RAM with Fast Page Mode Revision History Revision No History Draft Date 0A Initial Draft August 11,2001 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

IS41C16256C

Contextual Info: IS41C16256C IS41LV16256C 256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES DESCRIPTION •฀ TTL฀compatible฀inputs฀and฀outputs;฀tri-state฀I/O •฀ Refresh฀Interval:฀฀512฀cycles/8฀ms •฀ Refresh฀Mode฀:฀฀RAS-Only,฀CAS-before-RAS฀ CBR ,฀

km416c256bj

Contextual Info: DRAM MODULE_ / _ 1 Mega Byte KMM532256BW/BWG Fast Page Mode \? 256KX32 DRAM SIMM Using 256Kx16 DRAM, 5V G EN E R A L D ESCRIPTIO N FEATURES • Performance Range: The Samsung KMM532256BW is a 256K bit x 32 Dynamic RAM high density memory module. The

Contextual Info: IC41C16256 IC41LV16256 Document Title 256Kx16 bit Dynamic RAM with EDO Page Mode Revision History Revision No History Draft Date 0A 0B Initial Draft Revise for typo on page 20 August 9,2001 December 18,2001 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

sem 2105 16 pin

Abstract: sem 2105 IC SEM 2105 S D 0344C 0344C
Contextual Info: H ig h Perform ance gg 256KX16 Il A S4C 256K 16F0 CM OS DRAM H ig h Speed 256Kxl 6 CMOS D R A M F a st Pape M ode Preliminary Features • Read-modify-write • TTL-compatible, three-state I/O • JEDEC standard packages • Organization: 262,144 w ords by 16 bits

AS4C256K16FO-50JC

Contextual Info: AS4C256K16FO 5V 256Kx16 CMOS DRAM fast-page mode Features • Organization: 264,144 words x 16 bits • High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption - Active: 770 mW max (AS4C256K16FO-50)

km416c256bj

Contextual Info: DRAMMODULE- > M e g a B y te KMM532512BW/BWG Fast Page Mode / 512Kx32 DRAM SIMM Using 256Kx16 DRAM, 5V G E N E R A L D ESCRIPTIO N / FEATURES • Perform ance Range: T h e Sam sung K M M 5 3 2 5 1 2 B W is a 5 1 2K bit x 32

KM416C256AJ

Abstract: KMM532256AW MM5322
Contextual Info: KMM532256AW/WG Fast Page Mode 256KX32 DRAM SIMM Using 256Kx16 DRAM, 5V G E N E R A L D E S C R IP T IO N FEATURES The Samsung K M M 532256AW is a 256K bit x 32 • Performance Range: Dynamic RAM high density memory module. The Samsung K M M 532256A W consists of two C M OS

IC41C16256-35K

Abstract: 106 35K IC41C16256 IC41LV16256
Contextual Info: IC41C16256 IC41LV16256 Document Title 256Kx16 bit Dynamic RAM with EDO Page Mode Revision History Revision No History Draft Date Remark 0A 0B 0C Initial Draft Revise for typo on page 20 Add Pb-free package August 9,2001 December 18,2001 April 23,2004 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

Contextual Info: Preliminary information •■ AS4LC256K16E0 II 3.3V 256KX16 CMOS DRAM EDO Features • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits • H igh speed - 3 5 / 4 5 / 6 0 ns RAS access tim e - 1 7 / 2 0 /2 5 ns c o lu m n address access tim e - 7 / 1 0 / 1 0 ns CAS access tim e

HY514260B

Abstract: HY514260BJ
Contextual Info: •HYUNDAI H Y514260B 256KX16, C M O S D R A M w ith /2 C A S DESCRIPTION T his fam ily is a 4M bit d yn am ic RAM o rg an ized 26 2 ,1 4 4 x 16-bit con figu ration w ith C M O S D R A M s. T he c irc u it and pro ce ss de sig n a llow this d e vice to a ch ie ve high p e rfo rm a n ce and low p o w e r d issip a tio n . O p tio n a l fe a tu re s are a cce ss tim e 5 0 , 60

80C186

Abstract: EPROM AMD
Contextual Info: Systems in Silicon Am186ED Microcontroller 386-class performance, enhanced system integration, lower system cost, with a built-in DRAM controller AMD Embedded Processor Division, Am186ED Technical Overview Memory Market Update Systems in Silicon • DRAM prices crashing

Contextual Info: PF765-02 _SPC8104F Low Voltage VGA LCD Controller • DESCRIPTION The SPC8104 is a low power, mixed voltage video controller based on VGA architecture and optimized for driving a 640x480 LCD panel display. VGA standard mode functionality is supported using standard IBM VGA

Contextual Info: EPSON PF765-02 _ SPC8104F Low Voltage VGA LCD Controller • DESCRIPTION The SPC8104 is a low power, mixed voltage video controller based on VGA architecture and optimized for driving a 640x480 LCD panel display. VGA standard mode functionality is supported using standard IBM VGA