256X36 Search Results

Contextual Info: CMOS SyncBiFlFO 256x36x2, 512x36x2, 1,024x36x2 IDT723622 IDT723632 IDT723642 Hhtegiated Devize Technology, lie . NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES: • Free-running C LK A and CLKB may be asynchronous or

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: CMOS SyncBiFlFO 256x36x2, 512x36x2, 1024x36x2 IDT723622 IDT723632 IDT723642 Integrated D evice Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: In tegrated D e vice T e ch n o lo g y , Inc. CMOS Triple Bus SyncFIFOT With Bus-Matching 256x36x2, 512x36x2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: The errata notice on the last page describes corrections that have already been added to this document.

Contextual Info: Integrated D eviœ Technology, lie . CMOS SyncBiFIFO with Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 FEATURES: • Memory storage capacity: IDT723624—256 x 36 x 2 IDT723634-512 x 36 x 2 IDT723644-1,0 2 4 x 3 6 x 2 • Two independent clocked FIFOs buffering data in

Contextual Info: 1dt Integrated Device Technology, Inc. 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256x36x2, 512x36x2, 1,024 x 36 x 2 PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

Contextual Info: IDT723622 IDT723632 IDT723642 CMOS SyncBiFIFO 256x36x2, 512x36x2, 1024x36x2 Integrated Device Technology, Inc. Advance inform ation for the IDT723622 Final for the IDT723632 Advance inform ation f o r the IDT723642 • • • • • • • Program mable Alm ost-Full and Alm ost-Em pty flags

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO 256x36x2, 512x36x2, 1 ,02 4 x3 6 x 2 I dt PRELIMINARY IDT72V3622 IDT72V3632 IDT72V3642 Integrated Device Technology, Inc. FEATURES: • Memory storage capacity: IDT72V3622-256 x 36 x 2 1DT72V3632-512 x 36 x 2 IDT72V3642-1,024 x 36 X 2

B17C

Contextual Info: _ INTEGRATED DEVICE. IDT •b6E D 4025771 DGlBlb'i 4flT ADVANCED INFORMATION CMOS SyncBiFlFO IDT723622 256x36x2,1024x36x2 IDT723642 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident • Two independent clocked FIFOs buffering data in oppo­

bd-9b

Contextual Info: MOSEL- VITELIC MS76542 256x36x2 BIDIRECTIONAL FIFO Features Description • ■ ■ ■ ■ The MS76542 contains two FIFO buffers which operate in parallel but opposite directions for bidirectional data buffering. The two FIFO buffers are each organized as 256 words by 36 bits. The

K8D3216UBC-pi07

Abstract: K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
Contextual Info: Product Selection Guide Memory and Storage April 2005 MEMORY AND STORAGE SECTION A DRAM DDR2 SDRAM DDR SDRAM SDRAM RDRAM NETWORK DRAM MOBILE SDRAM GRAPHICS DDR SDRAM DRAM ORDERING INFORMATION FLASH NAND, OneNAND, NOR FLASH NAND FLASH ORDERING INFORMATION SRAM

736-Pin

Abstract: LSI coreware library 64X144
Contextual Info: ADVANCE DATASHEET RC1800 Foundation Slice Family July 2005 The RapidChip RC1800 Foundation Platform ASIC Family, except for the RC1812 slice, is in NO-NEW-DESIGN Status as of July 2005. LSI Logic is not accepting new designs in this slice Family. Information in this datasheet is

MachXO sysIO Usage Guide

Abstract: LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25
Contextual Info: MachXO Family Data Sheet Version 02.3_4W February 2007 MachXO Family Data Sheet Introduction April 2006 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

DSC5002

Contextual Info: 256K x 36, 512K x 18 2.5V Synchronous ZBTTM SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features u 256K x 36, 512K x 18 memory configurations u Supports high performance system speed - 200 MHz Address and control signals are applied to the SRAM during one

ORT8850

Abstract: ORT8850H ORT8850L STM-64 STS-192
Contextual Info: Preliminary Product Brief May 2000 ORCA ORT8850 Field-Programmable System Chip Introduction Field-programmable system chips FPSCs bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single device. Lucent Technologies Microelectronics Group

LC4064ZE

Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork
Contextual Info: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1

fifo asi cypress

Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 PRELIMINARY CYPRESS 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Fully asynchronous and sim ultaneous read and write operation permitted Mailbox bypass register for each FIFO Parallel and Serial Programmable Almost-Full and

PU86

Contextual Info: QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  16 quad clock networks per device Low Power Programmable Logic

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights  4 programmable global clock networks • Quadrant-based segmentable clock networks Low Power Programmable Logic  20 quad clock networks per device

QL1P100

Contextual Info: QuickLogic PolarPro Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  20 quad clock networks per device

AES1510

Abstract: aes2510 authentec ML67Q5250 ML67Q525 PB00X AuthenTec fingerprint XA06 XA04 XA05
Contextual Info: お客様各位 資料中の「沖電気」「ＯＫＩ」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株

723653

Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide

syscon

Abstract: LFEC1E-3T100C ips works 6CW3
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported

565 PLL

Abstract: linear application handbook national semiconductor pll 565 application CIII52001-1 EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55
Contextual Info: Section 1. Cyclone III Device Datasheet This section includes the following chapter: • Revision History Altera Corporation Chapter 1, Cyclone III Device Datasheet: DC and Switching Characteristics Refer to each chapter for its own specific revision history. For information on when each chapter was