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CMOS 16-Bit Priority Encoder

Abstract: P2800 DS4440 content addressable memory Wired mae p2800s
Contextual Info: COMMERCIAL-IN-CONFIDENCE P2800 FEBRUARY 1996 PRELIMINARY INFORMATION DS4468-1.0 P2800 2K x 64BIT MULTI-PORT CONTENT ADDRESSABLE MEMORY The P2800 2K x 64bit Multi-port Content Addressable Memory CAM is designed for address filtering, routing and translation applications in Ethernet, Token Ring, SMDS and

Contextual Info: Data Sheet May 27, 2005 TSI-2 2k x 2k Time-Slot Interchanger 1 Introduction This document consists of two major sections: „ The TTSI002081 device hardware description. This section contains ball information, operating conditions, dc electrical characteristics, timing diagrams, ac characteristics, and packaging information.

TAG 8446

Abstract: tag 8438 TAG 8426 TAG 8430 TXC-06920-MB TAG 8434 GMII VLAN Tag TSX 07 31 2428 error code cdb 400E structure of GMII packet with VLAN Tag
Contextual Info: TM Envoy-XE Device Metro Ethernet Switch TXC-06920 DATA SHEET PRELIMINARY TXC-06920-MB, Ed. 2 March 2006 FEATURES APPLICATIONS • IEEE 802.1Q compliant Ethernet switch supporting up to 8K Ethernet MAC addresses, 2K Active Network Tags VLANs, QTAG, MPLS or Martini and up to 2K

Contextual Info: Si GEC PLESSEY S 1' M I C. O l\ D l. PRELIMINARY INFORMATION 1 l K S P2800 2K X 64BIT MULTI-PORT CONTENT ADDRESSABLE MEMORY The P2800 2K x 64bit Multi-port Content Addressable Memory (CAM) is designed for address filtering, routing and translation applications in Ethernet, Token Ring, SMDS and

Contextual Info: 9Ë GEC PLESSEY F e b r u a r y 1997 PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS4468-2.2 P2800 2K x 64BIT MULTI-PORT CONTENT ADDRESSABLE MEMORY The P2800 2K x 64bit Multi-port Content Addressable Memory CAM is designed for address filtering, routing and

chilled water system

Contextual Info: Data Sheet, Revision 3 September 21, 2005 TSI-2 2k x 2k Time-Slot Interchanger 1 Introduction The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page 61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text

r2s3

Abstract: TDA 2025 chip TDA 2025 tda 2015 UTC 2025 P3TC HA 4016 Z8603 utc 1018 centrifuge machine for acceleration
Contextual Info: Zilog PRELIMINARY IN FO R M A TIO N P r o d u c t S p e c ific a tio n June 1987 Z8 Z8611 MCU Military Electrical Specification Z8603 Prototyping Device with 2K EPROM Interface F a a tu rM G e n ara l D e sc rip tio n • C om plete m icrocom puter, 2K 8601 or 4K

AMCC Evros

Abstract: hdlc tigris 31x31mm
Contextual Info: MyAMCC - Product Summary Home MyAMCC Contact Us Site Map Help Knowledge Center Tigris OC-48 S4811 Search 2.5GHz, 2k channels HDLC controller View All Products ✔ Search Products Framer/Mapper MISSION Network Processor MISSION Search Documents General Description

smd marking RA2 transistor

Abstract: Zener diode smd marking ck smd marking RA1 transistor SMD ZENER DIODE 73a smd zener diode code k2 TRANSISTOR SMD MARKING CODE 2t C1005y5v1c104zt PS2 Series connector Zener diode smd marking 27 PIC16CXX
Contextual Info: PIC16C62X EPROM-Based 8-Bit CMOS Microcontroller Devices included in this data sheet: Pin Diagrams • PIC16C620 • PIC16C621 • PIC16C622 PDIP, SOIC, Windowed CERDIP Device Program Memory Data Memory PIC16C620 512 80 PIC16C621 1K 80 PIC16C622 2K 128 •

HM62V8512LFP

Abstract: HM53861J M51419 16M dram dram zip 256kx16 m514280 hn27c1024hg 4M DRAM EDO M5241605 HM534253BT
Contextual Info: Memories Dynamic RAMs DRAM Access time ns 60 80 {HM5116100AS/ATS J F.P. 4k refresh -4Mx4 - {HM5116400AS/ATS ] F.P. 4k refresh 1HM51W16400AS/ATS ] F.P. 4k refresh 1HM5117400AS/ATS ] F.P. 2k refresh -3.3V operation- 16M- 70 -16Mx1 -3.3V operation— 2Mx8 -3.3V operation-

KMM536512B8

Abstract: KMM53651 KMM536512B
Contextual Info: KMM536512B DRAM MODULES 512KX36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM M 536512B is a 51 2K bit X 36 Dynamic RAM high density memory module. The Sam­ sung KM M 536512B consist of sixteen CMOS 2 5 6 K X 4

ldr 6k

Abstract: 200H MDT10P22 MDT10P23
Contextual Info: MDT10P23 AE 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 2K words EPROM and80 bytes static RAM. Four comparator inputs with external Vref

STI5500

Abstract: STi55 STi5500 st20 ST20 TOOLSET ST20C2 set top box block diagram LS 2027 Final Audio video rgb splitter amplifier schematic ST20 twin decoder A215
Contextual Info: STi5500 SET TOP BOX BACKEND DECODER WITH INTEGRATED HOST PROCESSOR PRELIMINARY DATA FEATURES • Enhanced 32-bit VL-RISC CPU - 50 MHz clock • fast integer/bit operation and very high code density ■ High performance memory/cache subsystem • 2 Kbytes Instruction cache, 2K bytes SRAM,

ldr 6k

Abstract: 200H 400H MDT2030
Contextual Info: MDT2030 AE 150 µs, 20 ms, 40 ms, 80 ms 1. General Description u This ROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve high programmable prescaler u speed, small size, the low power and high noise On chip memory includes 2K words EPROM, and

Contextual Info: $ M 28C17A ic r o c h ip 16K 2K x 8 CMOS EEPROM PACKAGE TYPE FEATURES • Fast Read Access Time— 150 ns • CMOS Technology for Low Pow er Dissipation - 30 m A Active - 100 (iA Standby • Fast Byte Write Time— 200 us or ms • Data Retention >10 years

27D014

Contextual Info: HM-92570 H A R R IS SEMICONDUCTOR 256K Buffered Synchronous CMOS RAM Module January 1992 Features Description • The HM-92570 is a fully buffered 256K bit CMOS RAM Module con­ sisting of sixteen HM-6516 2K x 8 CMOS RAMs, two 82C82 CMOS octal latching bus drivers, and two HCT-138 CMOS 3:8 decoders in

idt p28-2

Abstract: j32-1 32-PIN IDT 600 mil Plastic DIP P28-1 J321
Contextual Info: M OSEL MS7203/ 7204 2K x 9, 4K x 9 CMOS FIFO FEATURES DESCRIPTION • First-ln/First-O ut static RAM based dual port memory The M OSEL MS7203/7204 are dual-port static RAM based CM O S First-In/First-Out FIFO mem ories organized in nine-bit wide words. The devices are configured so that

49LF002A

Abstract: 2732 eprom 49lf003a N82802AB EPROM 271024 49lf004a IC 2732 pdf datasheet 6264 SRAM ic 6264 pdf datasheet 49LF008A
Contextual Info: WICE-8MA EPROM/SRAM Emulaor WICE-8MA Capacity Quantity Device Low voltage Device 2K 8 2 2716 4K 8 2 2732 8K 8 2 2764 16K 8 2 27128 32K 8 2 27256 64K 8 2 27512 128K 8 2 27010 27LV010 256K 8 2 27020 27LV020 512K 8 2 27040 27LV040 1024K 8 1 27080 27LV080 64K 16

TRANSISTOR 1383

Abstract: ST2064 74290 Counter he 8050 d transistor 002 545 18 05 LT 862 PAGE34 Sitronix W65C02S applicaion of sequence detector
Contextual Info: ST Sitronix ST2064 8 BIT Microcontroller with 64K bytes ROM PRELIMINARY Notice: This is not a final specification. Some parameters are subject to change. 1. FEATURES „ „ „ „ „ „ „ „ „ „ Totally static 65C02S CPU ROM: 64K x 8-bit RAM: 2K x 8-bit Stack: Up to 128-level deep

Contextual Info: M ic r o c h ip 2 8 1 A 7 16K 2K X 8 CMOS EEPROM PACKAGE TYPES FEATURES • Fast Read Access Time— 150 ns • CMOS Technology for Low Power Dissipation - 30 mA Active - 100 |iA Standby • Fast Byte Write Time— 200 us or 1 ms • Data Retention >200 years

MS7204-35PC

Abstract: LC 7204
Contextual Info: MOSEL MS7203/ 7204 2K x 9, 4K x 9 CMOS FIFO FEATURES DESCRIPTION • First-In/First-O ut static RAM based dual port m em ory The M O SEL M S7203/7204 are dual-port static RAM based CM OS First-ln/First-O ut FIFO m em ories organized in nine-bit wide words. The devices are configured so that

Contextual Info: $ 28C17A M ic r o c h ip 16K 2K x 8 CMOS EEPROM • Fast Read Access Time— 150 ns • CMOS Technology for Low Power Dissipation — 30 mA Active — 100 nA Standby • Fast Byte Write Time— 200 |is or 1 ms • Data Retention >10 years • High Endurance - Minimum 104 Erase/Write Cycles

Contextual Info: M 28C17A ic r o c h ip 16K 2K x 8 CMOS EEPROM PACKAGE TYPE FEATURES • Fast Read A ccess Time— 150 ns • CMOS Technology fo r Low P ow er Dissipation - 30 m A Active - 100 (iA S tandby • Fast Byte W rite Time— 200 |xs o r 1 ms • Data Retention >10 years

Contextual Info: H A R R HM-92560 IS S E M I C O N D U C T O R 256K Synchronous CMOS RAM Module January 1992 Features Description • Low Standby Current. 500|iA The HM-92560 is a high density 256K bit CMOS RAM module. Six­ teen synchronous HM-6516 2K x 8 CMOS RAMs in Leadless Chip