2MBITS DRAM Search Results
2MBITS DRAM Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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TMS4030JL |
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TMS4030JL - TMS4030 - DRAM, 4KX1, 300ns, MOS, CDIP22 |
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4164-15FGS/BZA |
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4164 - DRAM, 64K X 1, 3-STATE OUTPUTS, 150 NS ACCESS TIME - Dual marked (8201006ZA) |
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4164-12JDS/BEA |
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4164 - DRAM, 64K X 1, 3-STATE OUTPUTS, 120 NS ACCESS TIME - Dual marked (8201008EA) |
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4164-15JDS/BEA |
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4164 - DRAM, 64K X 1, 3-STATE OUTPUTS, 150 NS ACCESS TIME - Dual marked (8201006EA) |
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CDCV857ADGGG4 |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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2MBITS DRAM Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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s5l840fx
Abstract: S5L840F calmRISC16 P9336 and pin diagram of MMC 4017 CalmRISC-16 player audio to flash memoy s5l8 samsung i2s S5H5002
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S5L840F) S5L840F 76Kbytes 16bit CALMRISC16TM) 24bit MAC2424 CalmRISC16) s5l840fx calmRISC16 P9336 and pin diagram of MMC 4017 CalmRISC-16 player audio to flash memoy s5l8 samsung i2s S5H5002 | |
Contextual Info: HY5V52CFP 4 Banks x 2M x 32Bit Synchronous DRAM Document Title 4Bank x 2M x32Bit Synchronous DRAM Revision History Revision No. History Draft Date Remark Preliminary 0.1 Initial Draft May. 2003 0.2 1 Deleted Preliminary 2) Defined Input/Output Cap. Spec. |
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HY5V52CFP 32Bit x32Bit HY5V52CFP 456bit 90Ball | |
Contextual Info: HY5V52CFP 4 Banks x 2M x 32Bit Synchronous DRAM Document Title 4Bank x 2M x32Bit Synchronous DRAM Revision History Revision No. History Draft Date Remark Preliminary 0.1 Initial Draft May. 2003 0.2 1 Deleted Preliminary 2) Defined Input/Output Cap. Spec. |
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HY5V52CFP 32Bit x32Bit HY5V52CFP 456bit 90Ball | |
Contextual Info: Preliminary HY5V52CFP 4 Banks x 2M x 32Bit Synchronous DRAM Document Title 4Bank x 2M x32Bit Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft May. 2003 Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume |
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HY5V52CFP 32Bit x32Bit HY5V52CFP 456bit 152x32. | |
HY5V52CFContextual Info: HY5V52CF 4 Banks x 2M x 32Bit Synchronous DRAM Preliminary DESCRIPTION The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32. |
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HY5V52CF 32Bit HY5V52CF 456bit 152x32. 90Ball | |
HY5V52CFP
Abstract: HY5V52CFPH
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HY5V52CFP 32Bit HY5V52CFP 456bit 152x32. HY5V52CFPH | |
Contextual Info: HY5V52CF 4 Banks x 2M x 32Bit Synchronous DRAM Preliminary DESCRIPTION The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32. |
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HY5V52CF 32Bit HY5V52CF 456bit 152x32. 90Ball | |
Contextual Info: HY5V52CF 4 Banks x 2M x 32Bit Synchronous DRAM Document Title 4Banks x 2M x 32Bit Synchronous DRAM Revision History Revision No. History Draft Date Remark Preliminary 0.1 Initial Draft Sep.06.2002 0.2 2nd Generation Nov.11.2002 0.3 133MHz Speed Added Dec.13.2002 |
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HY5V52CF 32Bit 133MHz HY5V52CF 90Ball | |
Contextual Info: Preliminary HY5V52CF 4 Banks x 2M x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32. |
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HY5V52CF 32Bit HY5V52CF 456bit 152x32. 90Ball | |
rt500
Abstract: HY5V52CF
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HY5V52CF 32Bit HY5V52CF 456bit 152x32. 90Ball rt500 | |
msm6598
Abstract: Digital ECHO microphone mixing circuit MSM6295 MSM62* ADPCM AR76 2mbits dram
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MSC1157 MSA180 MSC1157 MSA180 msm6598 Digital ECHO microphone mixing circuit MSM6295 MSM62* ADPCM AR76 2mbits dram | |
M9842
Abstract: MSM62* ADPCM MSM63* ADPCM 5.3KHz IC
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E2D5004-27-50 30-pin 100-pin 56-pin MSM6588 6588L/6688/6688LV6789A/6789L. M66B8/6688L/6789A/6789L MSM6688L MSM6789L M9842 MSM62* ADPCM MSM63* ADPCM 5.3KHz IC | |
Contextual Info: UG4M23201PTCT G Data sheets can be downloaded at www.unigen.com 8M Bytes (2M x 32 bits) FPM MODE DRAM MODULE FPM Mode Unbuffered 72 Pin SIMM based on 4 pcs 1M x 16 DRAM with LVTTL, 1K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 72-Pin SIMM Pr |
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UG4M23201PTCT 72Pin 72-Pin DQ16-DQ31 | |
a1241
Abstract: NC143
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UG42W641 144-Pin 050mil) a1241 NC143 | |
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Contextual Info: UG42S6428GSG-PL Data sheets can be downloaded at www.unigen.com 16M Bytes 2M x 64 bits SYNCHRONOUS DRAM MODULE PC100 SDRAM Unbuffered SODIMM based on 8 pcs 2M x 8 SDRAM with LVTTL, 2 banks & 2K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 144-Pin SODIMM |
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UG42S6428GSG-PL PC100 UG42S6428GSG-PL 144-Pin | |
UG42S6442HSGContextual Info: UG42S6442HSG Data sheets can be downloaded at www.unigen.com 16M Bytes 2M x 64 bits SYNCHRONOUS DRAM MODULE PC100 SDRAM Unbuffered SODIMM based on 2 pcs 2M x 32 SDRAM with LVTTL, 4 banks & 4K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 144-Pin SODIMM |
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UG42S6442HSG PC100 144-Pin UG42S6442HSG-PL/PH UG42S6442HSG | |
Contextual Info: UG42T6442HSG-PL Data sheets can be downloaded at www.unigen.com 16M Bytes 2M x 64 bits SYNCHRONOUS DRAM MODULE PC133 SDRAM Unbuffered SODIMM based on 2 pcs 2M x 32 SDRAM with LVTTL, 4 banks & 4K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 144-Pin SODIMM |
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UG42T6442HSG-PL PC133 UG42T6442HSG-PL 144-Pin | |
MARKING U1Contextual Info: UG42S6442HSG Data sheets can be downloaded at www.unigen.com 16M Bytes 2M x 64 bits SYNCHRONOUS DRAM MODULE PC100 SDRAM Unbuffered SODIMM based on 2 pcs 2M x 32 SDRAM with LVTTL, 4 banks & 4K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 144-Pin SODIMM |
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UG42S6442HSG PC100 UG42S6442HSG-PL/PH 144-Pin MARKING U1 | |
Contextual Info: AL4V2M8221 AL4V2M8222 Data Sheet Revision V1.0 Preliminary Version Information furnished by AverLogic is believed to be accurate and reliable. However, no responsibility is assumed by AverLogic for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or |
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AL4V2M8221 AL4V2M8222 AL4V2M8221/AL4V2M8222 AL4V2M8221, AL4V2M8221/AL4V2M8222 | |
rgb to vga circuit
Abstract: LQFP208-P-2828 MN5815UB
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MN5815UB MN5815UB 18-bit rgb to vga circuit LQFP208-P-2828 | |
convert ega to vga
Abstract: rgb to vga circuit MN5815UB ega to vga VGA RGB LCD control host to vga convert LCD RGB 18 bit LQFP208-P-2828
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MN5815UB MN5815UB 18-bit convert ega to vga rgb to vga circuit ega to vga VGA RGB LCD control host to vga convert LCD RGB 18 bit LQFP208-P-2828 | |
875mil
Abstract: HY57V651610TC10
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HY57V651610 864-bit 152x16. 875mil HY57V651610TC10 | |
hy57v164010cContextual Info: HY57V164010C 2 Banks x 2M x 4 Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V164010C is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V164010C is organized as 2banks of |
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HY57V164010C HY57V164010C 216-bits 152x4. 400mil 44pin | |
8MX16
Abstract: HY5V26E
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128Mb 16bits 128Mbit 8Mx16bit) HY5V26E 728bit A10/AP 8MX16 |