875MIL Search Results

Contextual Info: ESMT M12L128168A 2M x 16 Bit x 4 Banks SDRAM Synchronous DRAM FEATURES ORDERING INFORMATION ! ! ! ! 54 Pin TSOP Type II (400mil x 875mil ) ! ! ! ! ! JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

E3235

Contextual Info: TOSHIBA TENTATIVE TC59WM815/07/03BFT-70,-75,-80 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS SYNCHRONOUS DYNAMIC RAM 8,388,608-WORDSX4BANKSX8-BITS SYNCHRONOUS DYNAMIC RAM 16,777,216-WORDSX4BANKSX4-BITS SYNCHRONOUS DYNAMIC RAM

lm814

Abstract: ID32-001
Contextual Info: TOSHIBA TC59LM814/06BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

dynamic ram binary cell

Abstract: QBA-1 qab1
Contextual Info: VIS Preliminary VG36643241AT CMOS Synchronous Dynamic RAM Description The device is CMOS Synchronous Dynamic RAM organized as 524,288 words x 32 bits x 4 banks. it is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only

DDR266

Contextual Info: DDR SDRAM stacked 1Gb B-die x4/x8 DDR SDRAM Stacked 1Gb B-die DDR SDRAM Specification (x4/x8) Revision 1.1 Rev. 1.1 August. 2003 DDR SDRAM stacked 1Gb B-die (x4/x8) DDR SDRAM st. 1Gb B-die Revision History Revision 0.0 (May, 2003) - First version for internal review.

K4S511632D

Contextual Info: K4S511632D CMOS SDRAM DDP 512Mbit SDRAM 8M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 July. 2002 This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,

K4S280432F

Abstract: K4S281632F
Contextual Info: SDRAM 128Mb F-die x4, x8, x16 CMOS SDRAM 128Mb F-die SDRAM Specification Revision 1.2 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.2 May 2004 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Revision History

K4S280432C

Abstract: K4S280432D
Contextual Info: K4S280432D CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Sept. 2001 K4S280432D CMOS SDRAM Revision History Revision 0.0 Mar., 2001

K4H511638B-TCCC

Abstract: K4H510838B-TCCC DDR333 DDR400 K4H511638B-T
Contextual Info: DDR SDRAM 512Mb B-die x8, x16 DDR SDRAM 512Mb B-die DDR400 SDRAM Specification Revision 1.0 Rev. 1.0 June 2003 DDR SDRAM 512Mb B-die (x8, x16) DDR SDRAM 512Mb B-die Revision History Revision 0.0 (May, 2003) - First release Revision 1.0 (June 2003) - Updated DC Characteristics

HY57V641620B

Abstract: HY57V651620B HY57V651620BLTC-55 HY57V651620BTC-10 HY57V651620BTC-10P HY57V651620BTC-10S HY57V651620BTC-55 HY57V651620BTC-6 HY57V651620BTC-7 HY57V651620BTC-75
Contextual Info: HY57V651620B 4 Banks x 1M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V641620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620B is organized as 4banks of 1,048,576x16.

ddr266

Contextual Info: DDR SDRAM 512Mb B-die x4, x8, x16 DDR SDRAM 512Mb B-die DDR SDRAM Specification Revision 1.1 Rev. 1.1 August 2003 DDR SDRAM 512Mb B-die (x4, x8, x16) DDR SDRAM 512Mb B-die Revision History Revision 0.0 (February, 2003) - First version for internal review

K4S561632C-TC/L75

Abstract: K4S561632C K4S561632C-TC K4S561632C-TC/L7C
Contextual Info: K4S561632C CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 Sept. 2001 K4S561632C CMOS SDRAM Revision History

DDR333

Abstract: DDR400 K4H281638E-TCCC
Contextual Info: DDR SDRAM 128Mb E-die x8, x16 DDR SDRAM 128Mb E-die DDR400 SDRAM Specification Revision 1.3 Rev. 1.3. September. 2003 DDR SDRAM 128Mb E-die (x8, x16) DDR SDRAM 128Mb E-die Revision History Revision 1.0 (February, 2003) - First release Revision 1.1 (February, 2003)

Contextual Info: 512Mb x16, DDP DDR SDRAM DDP 512Mbit DDR SDRAM 8M x 16bit x 4 Banks DDR SDRAM Specification Revision 1.0 July. 2002 This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,

HY57V281620A

Abstract: HY57V281620ALT-HI HY57V281620ALT-KI HY57V281620ALT-PI HY57V281620ALT-SI HY57V281620AT-HI HY57V281620AT-KI HY57V281620AT-PI HY57V281620AT-SI
Contextual Info: HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range . HY57V281620A is organized as 4banks of 2,097,152x16

HY57V56820BT-H

Abstract: HY57V56820B HY57V56820BT-6 HY57V56820BT-K
Contextual Info: HY57V12820 L T 4 Banks x 16M x 8Bit Synchronous DRAM DESCRIPTION The HY57V56820B is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820B is organized as 4banks of 16,777,216x8.

K4C560838C-TCB

Contextual Info: K4C5608/1638C 256Mb Network-DRAM Network-DRAM Specification Version 0.2 - 1 - REV. 0.2 Jan. 2002 K4C5608/1638C 256Mb Network-DRAM Revision History Version 0.0 Oct. / 5 / 2001 - First Release Version 0.1 (Dec. / 15 / 2001) - The product name is changed to Network-DRAM

K4H560838C-TCB3

Abstract: DDR200 DDR266A DDR266B DDR333 k4h560838ctcb3
Contextual Info: 256Mb C-die x4/8 DDR SDRAM DDR SDRAM Specification Version 0.7 - 1 - REV. 0.7 Jan. 31. 2002 256Mb C-die(x4/8) DDR SDRAM Revision History Version 0 (May, 2001) - First version for internal review of 256Mb C-die. Version 0.1 (July, 2001) - Updated target current spec(TSOP package base)

Contextual Info: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension

HY57V561620T

Abstract: HY57V561620
Contextual Info: HY57V561620T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V561620 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. HY57V561620 is organized as 4 banks of

Contextual Info: ESMT M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007)

Contextual Info: ESMT M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Revision 0.4 (01 Oct. 2007) - Modify IDD spec. Revision 1.0 (20 Nov. 2007) - Delete “Preliminary”

HY57V658020B

Abstract: HY57V658020BTC-10SI HY57V658020BTC-75I HY57V658020BTC-7I
Contextual Info: HY57V658020B 4 Banks x 2M x 8Bit Synchronous DRAM DESCRIPTION The Hynix HY57V658020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. HY57V658020B is organized as 4banks of 2,097,152x8.

K4S280432C

Abstract: K4S280432D
Contextual Info: K4S280432D CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.0 Mar. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Mar. 2001 K4S280432D CMOS SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM