3 INPUT OR GATES TTL Search Results

MC14075B

Abstract: MM54HC MM74HC 54HC 54LS 74HC 74HC4075 74LS CD4075B MM54HC4075
Contextual Info: MM54HC4075 MM74HC4075 Triple 3-Input OR Gate General Description Features These OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits All gates have buffered outputs providing

Contextual Info: LS TTL DN74LS Series DN74LS51 DN74LS51 bo 741*51 2-w ide 3-input, 2-w ide 2-input AND-OR-INVERT Gates • Description DN74LS51 contains tw o 2-input and tw o 3-input AND-ORINVERT gates. ■ Features • • • • Low pow er consum ption P d = 5.5mW typical

F10210

Abstract: F10211 F10610 F10611
Contextual Info: F10210 F10211l/» F10610"* F10611 DUAL 3-3 OR • DUAL 3-3 NOR FlOK VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION — The F10210 and F10610 are Dual 3-Input 3-O utput OR Gates and the F10211 and F10611 are Dual 3-Input 3-O utput NOR Gates. Each gate has three output transistors driven in parallel, with their emitters brought out on

Contextual Info: I LS TTL DN74LS Series DN74LS51 DN74LS51 2-w id e 3-input, 2-w id e 2-input AND-OR-INVERT Gates • Description P-1 DN74LS51 contains two 2-input and two 3-input AND-ORINVERT gates. ■ Features • Low power consumption P j = 5.5mW typical • High speed (tp<j = 12ns typical)

MM74HC4075

Contextual Info: January 1988 Semiconductor & MM54HC4075/MM74HC4075 Triple 3-Input OR Gate General Description Features These OR gates utilize advanced silicon-gate CMOS tech­ nology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS inte­

cd74HC32

Abstract: cd74hct32
Contextual Info: P *3 3 S CD54HCT32, CD74HC32, CD74HCT32 High Speed CMOS Logic Quad 2-Input OR Gate September 1997 Features Description • Typical Propagation Delay: 7ns at Vcc = 5V, C L = 15pF, Ta = 25°C The Harris CD74HC32, CD74HCT32 contain four 2-input OR gates in one package. Logic gates utilize silicon gate CMOS

74hct386

Contextual Info: GD54/74HC386, GD54/74HCT386 QUAD 2-INPUT EXCLUSIVE OR GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 3 8 6 . They contain four independent 2-input Exclusive OR gates. The HC/HCT 3 8 6 are electrically identical to the HC/HCT 8 6 , However,

74LS32 configuration

Abstract: 74hc32 74HC GD54HC32 GD74HC32 pin configuration logic symbol 74LS32 logic symbol 74LS32
Contextual Info: GD54/74HC32, GD54/74HCT32 QUAD 2-INPUT OR GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 3 2 . They contain four independent 2-input OR gates. These devices are characterized for operation over wide temperature ranges to meet in­

74LS32 configuration

Abstract: 74hc32 GD74HC32 74LS32 Quad 2-Input OR Gate 74HC logic symbol 74LS32 pin configuration logic symbol 74LS32 74HC LOGIC PINOUT 74LS32 pinout
Contextual Info: GD54/74HC32, GD54/74HCT32 QUAD 2-INPUT OR GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 3 2 . They contain four independent 2-input OR gates. These devices are characterized for operation over wide temperature ranges to meet in­

74HCT51

Abstract: GD74HCT51
Contextual Info: GD54/74HC51, GD54/74HCT51 DUAL AND-OR-INVERT GATES General Description These devices are identical in pinout to the 5 4/74L S 51 . They contain one 2-wide 2-input & one 2-wide 3-input AND-OR-INVERT gates. These devices are characterized for operation over wide

Contextual Info: DN74LS54 LS TTL DN74LS Series DN74LS54 4 - wide AND-OR-INVERT Gates P-1 • Description DN74LS54 contains four 2-input and four 3-input AND-ORINVERT gates. ■ Features • • Low power consumption Pd = 4.5mW typical High speed (tpci = 12ns) • Low output impedance

ECL 100102

Abstract: 100102F 100102DC LU58 ecl 10K signetics 100102f SIGNETICS 100102Y fiat ecu
Contextual Info: 100102 Signetics Gate Quint 2-Input OR-NOR Gate With Comm on Enable Product Specification ECL Products DESCRIPTION The 100102 has five 3-input gates. One input is a common enable to all five gates. TYPE TY PIC AL PROPAGATION DELAY TY PIC A L SUPPLY CURRENT

74LS58

Abstract: 74HCT58 GD74HC58 54/74LS58 74HC GD54HC58
Contextual Info: GD54/74HC58, GD54/74HCT58 DUAL AND-OR GATES General Description These devices are identical in pinout to the 54/74LS 58. They contain one 2-wide 2-input & one 2-wide 3-input AND-OR gates. These devices are characterized for operation over wide temperature ranges to meet industry and military

Contextual Info: N a ti o n a l January 1988 Semiconductor MM54HC4075/MM74HC4075 Triple 3-Input OR Gate General Description Features These OR gates utilize advanced silicon-gate CMOS tech­ nology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS inte­

MC14075B

Abstract: CD4075 74LS series logic gates 3 input or gate 74HC CD4075B MM54HC4075 MM74HC4075 MM74HC4075N MC14075
Contextual Info: January 1988 MM54HC4075/MM74HC4075 Triple 3-Input OR Gate General Description Features These OR gates utilize advanced silicon-gate C M OS te c h ­ nology to achieve operating speeds sim ilar to LS-TTL gates w ith th e low pow e r consum ption o f standard C M OS inte ­

CD4073

Abstract: CD4073BCN CD4076BCJ CD407SBCN CD4075BC
Contextual Info: CD4073BM/CD4073BC, CD4075BM/CD4075BC National Æ5m Semiconductor CD4073BM/CD4073BC Double Buffered Triple 3-Input AND Gate CD4075BM/CD4075BC Double Buffered Triple 3-Input OR Gate General Description Features These triple gates are monolithic complementary MOS •

HEF4075BP

Abstract: HEF4075B HEF4075BD HEF4075BT
Contextual Info: HEF4075B gates TRIPLE 3-INPUT OR GATE The HEF4075B provides the positive triple 3-input OR function. The outputs are fu lly buffered for highest noise immunity and pattern insensitivity of output impedance. foU^UizUHURJ^UeL *7 Vqd Ig ^8 D HEF4075B I4 Ib li

Contextual Info: LS TTL DN74LS Series DN74LS54 DN74LS54 Ì>N 7 4. L S 4 - wide AND-OR-INVERT Gates • Description P-1 DN 74LS54 contains four 2-input an d four 3-input AND-ORINV ERT gates. ■ Features • • • • Low pow er consum ption P j = 4.5mW typical High speed ( t p d = 12ns)

ic 7451 pin configuration

Abstract: 74 LS 00 Logic Gates
Contextual Info: 7451, LS51, S51 Signetics Gates '51, 'S51 Dual 2-Wide 2-Input AND-OR-lnvert Gate LS51 Dual 2-Wide 3-Input, 2-Wide 2-Input AND-OR-lnvert Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 7451 11ns 5.7mA 74LS51

CMOS 4000 Logic Family

Abstract: MN74HC4075 MN74HC4075S CMOS 4000 4000 series Cmos logic gate
Contextual Info: High-Speed CMOS Logic MN74HC Series m N 74H C 4075/ aaN74HC4075S MN74HC4075 MN74HC4075S Triple 3-Input OR Gates • P-1 Description MN74HC4075/MN74HC4075S contain three 3 -input positive isolation OR gate circuits. Adoption o f a silicon gate CMOS process has resulted in low

74ACT11086

Contextual Info: i TEXAS INSTR LOGIC 31E D M DDfia534 3 • T I I 3 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES ' T ' ({3 'Z -l~ o O TO 185— D3380, NOVEMBER 1989 Inputs are TTL-Voltage Compatible 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE

Contextual Info: Signelìcs 7451, LS51, S51 Gates '51, S51 Dual 2-Wide 2-Input AND-OR-lnvert Gate LS51 Dual 2-Wlde 3-Input, 2-Wide 2-Input AND-OR-lnvert Gate Product Specification Logic Products FUNCTION TABLE '51, ’S51, h 'LS51 TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

Contextual Info: 5 7 0 3 wo 5706 QUAD 2-INPUT PERIPHERAL/POWER DRIVERS -TRANSIENT-PROTECTED OUTPUTS These 16-lead quad 2-input peripheral/power drivers are bipolar monolithic integrated circuits containing AND or OR logic gates, highcurrent switching transistors, and transient-suppression diodes

5v constant power supply lob

Abstract: D107 DN74LS32
Contextual Info: LS TTL DN74LS Series DN74LS32 D N 74L S 32 î 3^ Quad 2 - input Positive OR Gates • D escription DN74LS32 contains four 2-input positive isolation OR gate circuits. P-1 H Features • • • • Low power consumption Pd = 20mW typical) High speed (tpd = 14ns typical)