311 PIN DIAGRAM Search Results

LM 311 IC

Abstract: pin diagram of LM 311 LM311L LM 311 ic 311 comparator LM211H IC LM 311 LM 211 P 211l
Contextual Info: LM111/211/311 Precision Voltage Comparator Distinctive Characteristics • • • • • The A M D LM 1 11/211/311 are functionally, electrically, and pin-for-pin equivalent to the National LM 111/211/311 Output Drive — 50V and 50m A Input Bias Current — 150nA max.

LM211H

Abstract: LM 311 IC LM311L LD311
Contextual Info: LM111/211/311 Precision Voltage Comparator Distinctive Characteristics • • The A M D L M 1 11/211/311 are functionally, electrically, and pin-for-pin equivalent to the National LM 111/211/311 O u tp u t Drive — 5 0 V and 50 m A • In put Bias C urrent — 150nA m ax.

LM311L

Abstract: LM311H LM311 V comparator 14 PIN DIAGRAM 311 comparator pin diagram LM211H LM 211 311 lm211d 14 dip amd am3 pin LM111L LM311 V comparator PIN DIAGRAM
Contextual Info: LM111/211/311 P re c is io n V o lta g e Com parator Distinctive Characteristics • • • • • The AM D LM 111/211/311 are functionally, electrically, and pir-for-pin equivalent to the National LM 111/211/311 „ _ . . Output Drive — 5 0 V and 50m A

Contextual Info: DS1647 PRELIMINARY DALLAS SEMICONDUCTOR DS1647 Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT • Integrated NV SRAM, real time clock, crystal, power fall control circuit and lithium energy source |1 3 2 1 Vcc A16 • A14 1 311 A15 A18 • Standard JEDEC bytewide 512Kx 8 static RAM pin­

Contextual Info: DS1750Y DALLAS SEMICONDUCTOR DS1750Y 3-Volt Partitionable 4096K NV SRAM FEATURES PIN ASSIGNMENT • 10 years minimum data retention in the absence of external power A18 I| 1 321 A16 I1 311 A15 • Data is automatically protected during power loss A14 I1 301

Contextual Info: DS1745Y DALLAS SEMICONDUCTOR DS1745Y 3-Volt Partitionable 1024K NV SRAM FEATURES PIN ASSIGNMENT • 10 years minimum data retention in the absence of external power • Data is automatically protected during power loss NC | 1 321 A16 1 2 311 I A15 A14 1 3

SW-311PIN

Contextual Info: RoHS Compliant Match GaAs SPST Switch, DC-3.0 GHz with TTL/CMOS Control Input SW-311-PIN V5 Features • • • • • • • • Integral TTL Driver Ultra Low Power Consumption Fast Switching Speed: 4 ns Typical Surface Mount Package 50 Ohm Nominal Impedance

Contextual Info: DS1647/DS1647LPM P R E L IM IN A R Y DS1647/DS1647LPM DALLAS SEMICONDUCTOR Nonvolatile Timekeeping RAM PIN ASSIGNMENT FEATURES • Integrated NV SRAM, real time clock, crystal, power fail control circuit and lithium energy source - 3 2 1 V cc 311 A15 A14 | 3

M513

Abstract: MASW-008845-0001TB SW-311-PIN
Contextual Info: SW-311-PIN Match GaAs SPST Switch, DC-3.0 GHz with TTL/CMOS Control Input Rev. V7 Features • • • • • • • • • Integral TTL Driver Ultra Low Power Consumption Fast Switching Speed: 4 ns Typical Hermetic Surface Mount Package 50 Ohm Nominal Impedance

wf vqc 10 d a6

Abstract: wf vqc 10 d 32-PIN 34-PIN DS1554 DS1554P DS9034PCX Y2KC Nonvolatile Timekeeping WF VQC 10
Contextual Info: DS1554 PRELIMINARY DALLAS SEMICONDUCTOR DS1554 256K NV Y2KC Timekeeping RAM PIN ASSIGNMENT FEATURES • Integrated NV SRAM, real tim e clock, crystal, p o w e rfail control circuit and lithium energy source RST | 1 NC ¡ 2 A14 [] 3 3 2 1 VCC 311 NC 3 0 1 IRQ/FT

Contextual Info: 401 54F/74F401 Connection Diagrams CRC Generator/Checker Description T l l I$ Redundancy Check (CRC Generator/Checker provides an advanc|pi|plJ&fttsnglementing the most widely used error detection scheme in4la|@taiapal data handling systems. A 3-bit control input

CRC 9401

Abstract: 311 pin diagram
Contextual Info: 401 54F/74F401 Connection Diagrams CRC Generator/Checker c p fT Z iN c c W | er p t r la Redundancy Check CRC Generator/Checker provides an lementing the most widely used error detection I data handling systems. A 3-bit control input 'g e n g jm j^ polynomials. The list of polynomials in­

74ls189 ram

Abstract: 74LS189 74LS189 logic diagram 74LS189DC 74LS189PC 74LS189FC 74S189DC 54LS189DM 54S189DM 74S189FC
Contextual Info: 189 CONNECTION DIAGRAM PINOUT A ¡4S/74S189 ►54LS/74LS189 b n 7 S 0 ao [T ï i ] Vcc 64-BIT RANDOM ACCESS MEMORY C sU m a. With 3-State Outputs we |T T7| A2 Di [7 Ö1 [ ? j l ] A3 02 ï D ESC R IPTIO N — The '189 is a high speed 64-bit RAM organized as a 16word by 4 -b it array. Address inputs are buttered to m inimize loading and are

Contextual Info: 175 54F/74F175 Connection Diagrams Quad D Flip-Flop Description The ’F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock

Contextual Info: 193 54F/74F193 Connection Diagrams Up/Down Binary Counter With Separate Up/Down Clocks Description The 'F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously

Contextual Info: 175 54F/74F175 Connection Diagrams Quad D Flip-Flop MR [ 7 '—' do [ 7 Description The ’ F175 is a high-speed quad D flip -flo p . The device is useful fo r general flip -flo p requirem ents where clo ck and cle ar in pu ts are com m on. The in fo rm atio n on the D inputs is stored during the LOW-to-HIGH clo ck

Contextual Info: 192 54F/74F192 Connection Diagrams Up/Down Decade Counter With Separate Up/Down Clocks —' pH Qi [T 3D vcc Tsl pc Q.-, [J Description The ’F192 is an up/down BCD decade 8421 counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the

Contextual Info: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop The ' f e | | J h | j eight edge-triggered D-type flip-flops with individual D inputs rf|tptots. The common buffered Clock CP and Master Reset (MR) in p u t! Idfecifiandfreset (clear) all flip-flops simultaneously.

Contextual Info: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop T— r ' - M R p ~ H rS rz a ht edge-triggered D-type flip-flops with individual D The common buffered Clock CP and Master Reset n ^ re s e i (clear) all flip-flops simultaneously. The register is full

Contextual Info: 164 54F/74F164 Connection Diagrams Serial-In, Parallel-Out Shift Register Description The ’F164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-toHIGH transition of the clock. The device features an asynchronous Master

Contextual Info: 784 54F/74F784 Connection Diagrams 8-Bit Serial-Parallel M ultiplier With Adder/Subtractor - Bn-1 [7 13 vcc pi u m y xsGE m *4 Description x2 [7 m The ’F784 is a serial nx8 -bit m ultiplier with a final stage adder/subtractor for optional use in adding a B bit to obtain S ± B. A (Bn.-|)-bit can also be

QN100

Contextual Info: 174 54F/74F174 Connection Diagrams Hex D Flip-Flop With Master Reset m r Description The ’F174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The

polynomials

Abstract: CRC-16 pin CRC-16 ccitt CRC-12 CRC-16 CRC16
Contextual Info: 401 54F/74F401 Connection Diagrams CRC Generator/Checker ‘ CPp~ p R e d u n d a n cy C h e ck CRC G e n e ra to r/C h e c k e r p ro vid e s an a d v a n c e r » ! ji f f ^ j o l e m e n t m g th e m o s t w id e ly use d e rro r d e te c tio n s c h e m e in C a f S t a ic r a l d a ta h a n d lin g s y s te m s . A 3 -b it c o n tro l in p u t

Contextual Info: 174 54F/74F174 Connection Diagrams Hex D Flip-Flop With Master Reset Description The ’F174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The