3117* INTEL Search Results

Contextual Info: T7110 Synchronous Protocol Data Formatter with Serial Interface Features Host Interface • C om patible with AT&T’s WE 32100 M icroprocessor and with Intel’s ¡APX86 and M otorola’s MC68000 m icroprocessor series ■ O n-chip 16-channel DMA memory address

intel 8087 architecture

Abstract: sahf instruction intel 8086 Arithmetic and Logic Unit -ALU 8087 coprocessor architecture 8086 instruction set 8086 opcode sheet free binary numbers multiplication 8088 instruction set intel 8086 opcode sheet procedure for converting to opcodes in 8086
Contextual Info: Floating-Point Unit 31 The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floatingpoint processing algorithms and exception handling architecture defined in the IEEE 754 and 854

15.4 lcd

Abstract: IBM LCD Connector U990 J503 lcd connector J513
Contextual Info: discrepancies between any succeeding product and this manual. Copyright c 2005 SAMSUNG Electronics Co.,Ltd. All rights reserved. Under the copyright laws, this manual cannot be reproduced in any form without the prior written permission of SAMSUNG Electronics Co.,Ltd. No

SSF3117

Abstract: on and off power switch dimension 1100
Contextual Info: SSF3117 DESCRIPTION The SSF3117 uses advanced trench technology to provide excellent RDS ON and low gate charge . A Schottky diode is provided to facilitate the implementation of a bidirectional blocking switch, or for DC-DC conversion applications. GENERAL FEATURES

MSP430F5326

Abstract: MSP430 data loggers
Contextual Info: MSP430F5326-DIE www.ti.com SLAS890 – AUGUST 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 2 • • • • Low Supply-Voltage Range: 1.8 V to 3.6 V Ultralow Power Consumption – Active Mode AM : All System Clocks Active – Standby Mode (LPM3):

CY7C292-50PC

Abstract: CY7C291 57c291 CY7C292-50
Contextual Info: CY7C291 _CY7C292 — .w Ä ^ SEMICONDUCTOR Reprogrammable 2048 x 8 PROM Features • W indowed for reprogramm ability • C ap a b le o f w ith stan d in g > 2000V' s ta tic d isch arg e • C M O S for optimum speed /pow er

AMD 22V10

Abstract: EPROM 27256 programmer schematic application PAL 16v8 ip8254 16v8 programming Guide C2503 22v10 pal 0001FFFFH eeprom programmer schematic 27256 EPROM intel 27256
Contextual Info: IDT79R3051 SYSTEM DESIGN EXAMPLE APPLICATION NOTE AN-86 APPLICATION NOTE AN-86 IDT79R3051 SYSTEM DESIGN EXAMPLE Integrated Device Technology, Inc. by Andrew Ng even further. Although the board is not populated with parts that have the highest performance achievable, its design can

ic 8255A

Abstract: intel ic 8255 Peripheral interface 8255 with ADC 8255A 8255 intel microprocessor block diagram ppi PPI 8255A PPI 8255 pin configuration PPI 8255 interface ic 8255 PPI intel 8255a ppi block diagram
Contextual Info: intJ 8255A/8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE • M C S -85T M Compatible 8255A-5 ■ Direct Bit Set/Reset Capability Easing Control Application Interface ■ 24 Programmable I/O Pins ■ Completely TTL Compatible ■ Reduces System Package Count ■ Fully Compatible with Intel

Contextual Info: * CYPRESS ADVANCED INFORMATION CY7C375Ì UltraLogic 128-Macrocell Flash CPLD Features speed CPLDs. Like all members of the F lash 370 i family, the CY7C375i is de­ • 128 macrocells in eight logic blocks • 128 I/O pins • 6 dedicated inputs including 4 clock

mil-std-1553b SPECIFICATION

Abstract: honeywell dcs manual smd code A1t MIL-STD-1773 A1t smd TSI S 14001 1553 SUmmit me 555 AS1773 UT69151
Contextual Info: S f.lMMIT TM Reference Manual Aeroflex Colorado Springs 4350 Centennial Blvd. Colorado Springs, CO 80907 719-594-8000, 719-594-8468 fax www.aeroflex.com/radhard SJ.1MMITTMReference Manual Table of Contents Overview Presentation Section 1 Engineering Notebooks

Burroughs Self-Scan

Abstract: B255A Peripheral interface 8255 with ADC Burroughs D504D 8255a PPI 8255 interface keyboard interfacing with 8255 microprocessors WM-71 PPI 8255 interface word control logic controller
Contextual Info: intJ 8255A/8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE • MCS-85TM Compatible 8255A-5 ■ 24 Programmable I/O Pins ■ Direct Bit Set/Reset Capability Easing Control Application Interface ■ Completely TTL Compatible ■ Reduces System Package Count ■ Fully Compatible with Intel

vfo 200v 0.4kw

Abstract: dipipm dipipm application note
Contextual Info: <Dual-In-Line Package Intelligent Power Module> MOSFET Super mini DIPIPM APPLICATION NOTE PSM03S93E5-A / PSM05S93E5-A Table of contents CHAPTER 1 INTRODUCTION .2

city 4OX

Contextual Info: AMDB AMD-K6 E High-Performance, AMD-K6 Embedded Processor DISTINCTIVE CHARACTERISTICS • Advanced 6-Issue RISC86 Superscalar Microarchitecture - Seven parallel specialized execution units - Multiple sophisticated x86-to-RISC86® instruction decoders - Advanced two-level branch prediction

40ebl

Contextual Info: Data Sheet January 1992 ATT7C183 ATT7C184 ^ A T fiT Microelectronics High-Speed CMOS SRAM 128 Kbit 2 x 4K x 16 or 8K x 16 Cache-Data Features • High-speed — 25 ns maximum access time Plug-compatible with Cypress CY7C183/184 ■ Direct map or two-way set associative

RE 5 TA

Abstract: CY7C281
Contextual Info: CY7C281 CY7C282 " s CYPRESS 1024 x 8 PROM SEMICONDUCTOR Features • C M O S for optimum sp eed / power • High speed — 30 ns commercial — 45 ns (military) • Low power — 495 mW (commercial) — 660 mW (military) • E P R O M technology 100% programmable

0x77C

Abstract: iodelay IEEE1722 DS818 KC705 RGMII phy Xilinx UG474 UG777 UG472 verilog code for mdio protocol
Contextual Info: ‘‘‘‘‘‘‘‘Tri-Mode LogiCORE IP Tri-Mode Ethernet MAC v5.3 DS818 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Tri-Mode Ethernet Media Access Controller TEMAC solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet

ZX-01

Abstract: T48I QD004
Contextual Info: P L X TECHNOLOGY CORP SSE D • bfi5514R D00ÜM13 'ÎSE mPLX EISA 9020BV T T 5 2 . '3 3 - 5 5 EISA Bus Master Interface Chip fo r Intel 82596 LAN Controller APRIL 1992 Patent Pending_ Features_ General Description_

BJ 131-6

Abstract: intel 82596 BUK 155 adapter block diagram b055 82596SX
Contextual Info: P L X TECHNOLOGY CORP 5 EE D • bñSSmT DOGOMIB ' ISE * P L X EISA 9020BV " T 5 a . '3 3 - S 5 EISA Bus Master Interface Chip fo r Intel 82596 LAN Controller APRIL 1992 Patent Pending_ Features_ General Description_

Contextual Info: HB54R1G9F2-A75B/B75B/10B 1 GB Registered DDR SDRAM DIMM 128-Mword x 72-bit, 2-Bank Module 36 pcs of 64 M × 4 Components E0089H20 (Ver. 2.0) Preliminary Mar. 30, 2001 Description The HB54R1G9F2 is a 64M × 72 × 2-bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of

ip8254

Abstract: AMD 22V10 Xceive 79r3001 Bf8000 EPROM 27256 programmer schematic IDT79R3051 R3000 R3051 R3052
Contextual Info: IDT79R3051 SYSTEM DESIGN EXAMPLE  APPLICATION NOTE AN-86 APPLICATION NOTE AN-86 IDT79R3051 SYSTEM DESIGN EXAMPLE Integrated Device Technology, Inc. by Andrew Ng even further. Although the board is not populated with parts that have the highest performance achievable, its design can

LC 7258

Abstract: C-274
Contextual Info: bSE D C Y P R ES S S E M I C O N D U C T O R SSÖRbbE QQ1GS50 T M «CYP CY7C271 CY7C274 CYPRESS SEMICONDUCTOR Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • Highspeed •— 30 ns commercial •— 35 ns (military)

I8255A

Abstract: 8255a 8225A
Contextual Info: in te i 8 2 5 5 A /8 2 5 5 A -5 PROGRAMMABLE PERIPHERAL INTERFACE MCS-85 Com patible 8255A-5 24 Programmable I/O Pins Direct Bit S e t/R e s e t Capability Easing Control Application Interface Com pletely TTL Com patible Reduces System Package Count Im proved DC Driving Capability

intel 8255a ppi block diagram

Abstract: intel IC 8255 8255 intel microprocessor block diagram ic 8255 intel Peripheral interface 8255 with ADC PPI 8255A ic 8255A 8255a PPI keyboard interfacing with 8255 microprocessors 8255 PPI INTEL
Contextual Info: in te l. 8 2 5 5 A /8 2 5 5 A -5 PROGRAMMABLE PERIPHERAL INTERFACE MCS-85 Com patible 8255A-5 24 Program m able I/O Pina • D irect B it S et/R eset C apability Easing C ontrol A pplication Interface C om pletely TTL Com patible ■ Reduces System Package Count

8255 intel microprocessor block diagram ppi

Abstract: intel 8255A Peripheral interface 8255 with ADC 8255A intel IC 8255 intel 8255 8255a intel keyboard interfacing with 8255 microprocessors Control word 8255 PPI datasheet intel IC 8255
Contextual Info: inU 8 2 5 5 A /8 2 5 5 A -5 PROGRAMMABLE PERIPHERAL INTERFACE • M C S - 8 5 TM Compatible 8255A-5 ■ 24 Programmable I/O Pins ■ Direct Bit Set/Reset Capability Easing Control Application Interface ■ Completely TTL Compatible ■ Reduces System Package Count