XCEIVE Search Results

Contextual Info: G8880DI Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)-40 Maximum Operating Temp (øC)85 Package StyleDIP Mounting StyleT Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

Contextual Info: G8880E Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)70 Package StyleQCC-J Mounting StyleS Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

xc3028

Abstract: xceive XC3028 Xceive DVB-T Tv tuner Diagram DVB-T DVB-T Tv tuner 9528 DVB-T Schematic DVB-T tuner diagram Digital TV receivers
Contextual Info: Product Brief Intel CE 9528 DVB-T TNIM Reference Design Consumer Electronics DVB-T Digital Terrestrial Front-end Solution with Xceive* Tuner • DVB-T set top boxes Intel® CE 9528 DVB-T Reference Design with Xceive* Tuner • DVB-T integrated digital TV

Contextual Info: G8880PI Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)70 Package StyleDIP Mounting StyleT Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

Contextual Info: G8880CI Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)-40 Maximum Operating Temp (øC)85 Package StyleDIP Mounting StyleT Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

Contextual Info: X7 Smart Tuner Product Brief X7 Smart Tuner ™ Worldwide Multi-Standard Hybrid Smart TV Tuner Overview The X7 Smart Tuner™ is the 4th generation of Xceive Smart Tuner™ family, now implemented in low cost CMOS process. The unique and patented Smart Tuner™ architecture combines a ver y high performance

Contextual Info: G8880C Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)70 Package StyleDIP Mounting StyleT Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

Contextual Info: G8880EI Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)-40 Maximum Operating Temp (øC)85 Package StyleQCC-J Mounting StyleS Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

Contextual Info: G8880D Linear ICs DTMF Circuit status Nom. Supp V 5.0 Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)70 Package StyleDIP Mounting StyleT Pinout Equivalence Code20-42 # Pins20 Ckt. (Pinout) NumberLN02000042 DescriptionIntegrated DTMF XCeiver;uP Port

MOTOROLA ONCORE UT plus

Abstract: hp 35821 6132 RAM 731 motorola MPCPRGREF/D LG E50 MPC8xx QMC SMC microcode MPC857DSL MPC857T MPC862
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MPC862UM/D 09/2002, REV 2 MPC862 PowerQUICC Family User’s Manual Supports MPC862P MPC862T MPC857T MPC857DSL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

MC68B21CP

Abstract: xcm916x1cth16 transistor marking code 12W SOT-23 sg379 MC68B54P XC68HC805P18CDW mc68b50cp MC2830 NE555N CHN NE555N
Contextual Info: SG379/D REV 7 Semiconductor Products Sector NORTH AMERICA SALES AND DISTRIBUTION PRICE LIST THIS BOOK IS IN COMPUTER SORT PRODUCT CLASSIFICATION – Please see General Information Section 1.3 EFFECTIVE DATE: JANUARY 10, 1998 General Information 1 Cross References

TX39

Abstract: VDD06 R3000A MIPS R3000A
Contextual Info: 66038 RC2160997 Frame 2 Page 1 Thursday, October 30, 1997 11:31 AM TOSHIBA TMP3912U 32-Bit MIPS RISC Processor Description Development Tool Support The TMP3912U is a single-chip, highly integrated Application Specific System Product ASSP developed specifically for

PEB3265

Abstract: PEB4266 DUSLIC application notes PEB4266 PEB2091 C165H C166 PEB82902 PEB82912
Contextual Info: Product Brief The C165H is a new low-cost member of the Infineon Communication Controller family. The device combines the successful Infineon C166 16-bit full static core with four independent HDLC controllers, IOM -2 interface and 3-KByte of on-chip Dual-Port RAM. The C165H

22716 transistor

Abstract: P-TQFP-144
Contextual Info: P R O D U C T B R I E F PEB 55508 IVAX-D PEB 22720 (IVAX-A0) PEB 22716 (IVAX-L2) IVAX ADSL Transceiver Chipset The IVAX ADSL transceiver chipset supports ADSL data transmission according to ITU-T standards G.dmt and G.lite. With industries lowest board space requirements and a power consumption of less than 1 W/ch, the new IVAX ADSL transceiver chipset fulfills all requirements for highly

k 4431

Contextual Info: in te i 28F200BX-T/B, 28F002BX-T/B 2 MBIT 128K x 16,256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x6/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Very High-Performance Read — 60/80 ns Maximum Access Time

MIPS R3000A

Abstract: R3000A TMPR3912U lcd 16*4 TMPR3922U TX39 toshiba DVD power supply pcmcia toshiba TC351
Contextual Info: TOSHIBA PRELIMINARY Description The TMPR3922U 32-bit MIPS RISC processor is a single-chip integrated digital Application Specific Standard Product ASSP for use with such devices as Hand-held PCs (HPC), PalmPCs, TV Set-Top Boxes (STB), DVD players, Webphones, Auto PC devices, and

AMD 22V10

Abstract: EPROM 27256 programmer schematic application PAL 16v8 ip8254 16v8 programming Guide C2503 22v10 pal 0001FFFFH eeprom programmer schematic 27256 EPROM intel 27256
Contextual Info: IDT79R3051 SYSTEM DESIGN EXAMPLE APPLICATION NOTE AN-86 APPLICATION NOTE AN-86 IDT79R3051 SYSTEM DESIGN EXAMPLE Integrated Device Technology, Inc. by Andrew Ng even further. Although the board is not populated with parts that have the highest performance achievable, its design can

PC87560UBD

Abstract: 8038 ic pin diagram for fm N82077 uPD765A 8038 signal generator chip DS1287 PC87550 PC87570 PD765A Tri-State Buffer CMOS
Contextual Info: November 1997 PC87560UBD — PCI System I/O 1.0 General Description 2.0 Features The PC87560 is a highly integrated IC which incorporates PCI Interface, Bus Mastering Fast IDE Controller, Universal Serial Bus USB Host Controller, commonly-used I/O peripherals, and power management functions. When used in

p45 connector

Abstract: 52521 RAM 2114 D-10 D-12 D-16 MPC855T MPC860 PA15 Socket AM2
Contextual Info: MPC855TUM/D 4/2002 REV 0.1 MPC855T User’s Manual Integrated Communications Microprocessor HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.

Contextual Info: NLAS4685 Pr oduct Preview Ultra−Low Resistance Dual SPDT Analog Switch The NLAS4685 is an advanced CMOS analog switch fabricated in Sub−micron silicon gate CMOS technology. The device is a dual Independent Single Pole Double Throw SPDT switch featuring

Contextual Info: A P P L I C AT I O N N OT E Coordinated Circuit Protection for USB Applications solutions for USB applications. This paper gives an overview of USB 3.0 requirements and presents typical circuit protection solutions for USB applications. This includes a coordinated

MIPS R3000A

Abstract: SN00177 SN00174 16X16 BIT RISC PROCESSOR MIPS r3000 Nihon Dempa Kogyo Co., Ltd. CS4216 LQFP208 philips monochrome monitor PR31500ABC
Contextual Info: INTEGRATED CIRCUITS MIPS PR31500 Poseidon embedded processor Preliminary specification Version 0.1 Philips Semiconductors 1996 Sep 24 Philips Semiconductors Preliminary specification MIPS PR31500 Poseidon embedded processor Version 0.1 GENERAL DESCRIPTION

SA1381

Abstract: SS823 RDATA13 3RA61 AC21T n25h VSS1490 bwd9 HAD44 HAD48
Contextual Info: A B C D REVISIONS ZONE LTR CN8237/CX29704 PCB:BT01-D255-011 A DESCRIPTION INITIAL APPROVED DATE RELEASE 1 1 DL1 DELAYLINE 2.5NS 1 2 U7 3 CN8237 SEGMENTATION SCLK0 R124 18 DL2 B3SCLK0 A3SCLK1 R116 18 DELAYLINE 2.5NS POWER VDD PINS E7, E8, E11, E12, E15, E16

PM835

Abstract: DDR PHY ASIC PM8355 infiniband PHY
Contextual Info: PM8355 QuadPHY-II Advance 4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support GENERAL DESCRIPTION SERIAL I/O TEST FEATURES The QuadPHY-II™ is a physical layer transceiver ideal for systems requiring high speed point-to-point communication links. It is applicable for PMAPMD connections in 10 GE, Infiniband 1