32K X 8 FLASH Search Results

Atmel AT24C Truncation Code

Abstract: marking ATML AT24C64D ATMEL marking code AT24C Atmel PART DATE CODE at24c AT24C64D-SSPD-T AT24C32D 24C32-64DAM AT24C32D-XPD-T atml 122
Contextual Info: Atmel AT24C32D and Atmel AT24C64D I2C Automotive Temperature Serial EEPROM 32K 4096 x 8 , 64K (8192 x 8) DATASHEET Features  Standard-voltage operation  VCC = 2.5V to 5.5V  Automotive temperature range –40C to 125C  Internally organized 4096 x 8 (32K), 8192 x 8 (64K)

ATMEL SERIAL EEPROM truncation code

Abstract: AT24c32d-sspd 24C32-64DAM AT24C32D atmel 32d
Contextual Info: Atmel AT24C32D and Atmel AT24C64D I2C Automotive Temperature Serial EEPROM 32K 4096 x 8 , 64K (8192 x 8) PRELIMINARY DATASHEET Features  Standard-voltage operation  VCC = 2.5V to 5.5V  Automotive temperature range –40C to 125C  Internally organized 4096 x 8 (32K), 8192 x 8 (64K)

Contextual Info: Atmel AT24C32D and Atmel AT24C64D I2C Automotive Temperature Serial EEPROM 32K 4096 x 8 , 64K (8192 x 8) PRELIMINARY DATASHEET Features  Standard-voltage operation  VCC = 2.5V to 5.5V  Automotive temperature range –40C to 125C  Internally organized 4096 x 8 (32K), 8192 x 8 (64K)

Contextual Info: Dense-Pac Microsystems, Inc. DPZ32X32V 32K X 32 FLASH Memory VERSAPAC O PRELIMINARY DESCRIPTION: The D PZ32X 32V is a 32K x 32 FLASH electrically erasable and programmable read only memory module built with four 32K x 8 FLASH memory devices. The module is a 66-pin P G A

24C64 WP

Abstract: 24c32 wp 24C64 AT 24C64 EEPROM bl24c64 BL24C32
Contextual Info: Shanghai Belling Corp., Ltd BL24C32/64 BL24C32/BL24C64 32K bits 4096 X 8 / 64K bits (8192 X 8) Two-wire Serial EEPROM Features Two-wire Serial Interface VCC = 1.8V to 5.5V Bi-directional Data Transfer Protocol Internally Organized BL24C32, 4096 X 8 (32K bits)

AT 24C64 EEPROM

Contextual Info: LESHAN RADIO COMPANY, LTD. 32K bits 4096 X 8 / 64K bits (8192 X 8) Two-wire Serial EEPROM Two-wire Serial EEPROM LR 24C32/LR 24C64 Features Two-wire Serial Interface VCC = 1.8V to 5.5V Bi-directional Data Transfer Protocol Internally Organized LR24C32, 4096 X 8 (32K bits)

EPROM

Abstract: M87C512 m27c256 UV EPROM ET2716
Contextual Info: GENERAL INDEX EPROM DEVICES NMOSEPROM M/ET2716 2K x 8 M2732A (4K x 8) M2764A (8K x 8) M27128A (16K x 8) M27256 (32K x 8) M27512 (64K x 8) UV EPROM . UV EPROM .

IC1210

Abstract: M28F256 PLCC32 QR108 TR08
Contextual Info: QUALIFICATION REPORT M28F256 256K 32K x 8 CMOS T5-U20 FLASH MEMORY in PLCC32 INTRODUCTION The M28F256 is a 256K FLASH Memory organised as 32K x 8 bits. It is manufactured in the SGS-THOMSON Advanced CMOS 0.8 micron T5-U20 (-20% upgrade) process which has been especially developed

TR08

Abstract: M28F256 PLCC32 QR108
Contextual Info: QUALIFICATION REPORT M28F256 256K 32K x 8 CMOS T5-U20 FLASH MEMORY in PLCC32 INTRODUCTION The M28F256 is a 256K FLASH Memory organised as 32K x 8 bits. It is manufactured in the SGS-THOMSON Advanced CMOS 0.8 micron T5-U20 (-20% upgrade) process which has been especially developed

A625308A

Abstract: A625308A-70S A625308AM-70S A625308AV-70S
Contextual Info: A625308A Series Preliminary 32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue February 2, 2001 Preliminary February, 2001, Version 0.0 AMIC Technology, Inc. A625308A Series

X28HC256 DIE

Abstract: X28HC256EMB-90 N 341 AB X28HC256 X28HC256DI-15 X28HC256DM-15 X28HC256DMB-15 X28HC256EMB-15 X28HC256FMB-15 X28HC256J-15
Contextual Info: X28HC256 256k, 32k x 8-Bit Data Sheet May 7, 2007 5V, Byte Alterable EEPROM Features The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing

Contextual Info: X28HC256 256k, 32k x 8-Bit Data Sheet September 21, 2011 5V, Byte Alterable EEPROM Features The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing

LP61L256CS-12

Abstract: LP61L256CS-15 LP61L256C LP61
Contextual Info: LP61L256C Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue November 9, 2001 Preliminary November, 2001, Version 0.0 AMIC Technology, Inc.

A615308

Abstract: A615308-12 A615308S A615308S-12 A615308V A615308V-12
Contextual Info: A615308 Series Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Initial issue January 17, 2001 January, 2001, Version 0.0 Remark AMIC Technology, Inc.

AMIC Technology

Abstract: A61L5308S-10 A61L5308S-12 A61L5308S-8 A61L5308V-8 A61L5308V-12 28LSOJ
Contextual Info: A61L5308 Seríes AMIC 32K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. History Issue Date 1.0 Initial issue February 06,1998 1.1 Modify 28-pin TSOP package outline drawing and dimensions

x25256

Abstract: sck 084 X24C16 SCK 102
Contextual Info: Preliminary Information X25256 256K 32K x 8 Bit 5MHz SPI Serial E2PROM with Block Lock Protection FEATURES ro The X25256 is a CMOS 256K-bit serial E2PROM, internally organized as 32K x 8. The X25256 features a Serial Peripheral Interface SPI and software protocol

A62L256

Abstract: A62L256-55LL A62L256-70LL A62L256M-55LL A62L256M-70LL A62L256R-55LL A62L256V-55LL
Contextual Info: A62L256 Series 32K X 8 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY Document Title 32K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date 1.0 Initial issue September 01, 1997 1.1 Modify 28-pin DIP, SOP and TSOP packages outline January 20, 1998

A62L256

Abstract: A62L256-55LL A62L256-70LL A62L256M-55LL A62L256R-55LL A62L256V-55LL
Contextual Info: A62L256 Series AMIC 32K X 8 BIT LO W VOLTAGE CMOS SRAM PRELIMINARY Document Title 32K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History History Issue Date 1.0 Initial issue September 01,1997 1.1 Modify 28-pin Rev. No. DIP,SOP and TSOP packages outline Remark

A62L256

Contextual Info: A62L256 Series Preliminary 32K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 32K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date 1.0 Initial issue September 01, 1997 1.1 Modify 28-pin DIP, SOP and TSOP packages outline January 20, 1998

A62L256

Contextual Info: A62L256 Series Preliminary 32K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 32K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date 1.0 Initial issue September 01, 1997 1.1 Modify 28-pin DIP, SOP and TSOP packages outline January 20, 1998

A625308A

Abstract: A625308A-70S A625308A-70SI A625308AM-70S A625308A-S A625308AV-70S
Contextual Info: A625308A Series Preliminary 32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package type November 7, 2001

A625308A

Abstract: A625308A-70S A625308A-70SU A625308AM-70S A625308AM-70SU A625308A-S A625308A-SU A625308AV-70S
Contextual Info: A625308A Series Preliminary 32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package type November 7, 2001

A615308

Abstract: A615308-12 A615308S-10 A615308S-12 A615308V-10 A615308V-12
Contextual Info: A615308 Series 32K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. History Issue Date 1.0 Initial issue March 12, 1998 1.1 Modify 28-pin TSOP package outline drawing and dimensions June 17, 1998

A61L5308S-10

Abstract: A61L5308S-12 A61L5308S-8 A61L5308V-10 A61L5308V-8
Contextual Info: A61L5308 Series 32K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. History Issue Date 1.0 Initial issue February 06, 1998 1.1 Modify 28-pin TSOP package outline drawing and dimensions June 17, 1998