36MB Search Results

EDI9G361024C

Contextual Info: EDI9G361024C 1024K x 36 Static RAM CMOS, High Speed Module FEATURES DESCRIPTION n 1024K x 36 bit CMOS Static The EDI9G361024C is a high speed 36Mb Static RAM module organized as 1024K words by 36 bits. This module is constructed from nine 1024K x 4 Static RAMs in SOJ packages on an epoxy

GS8342Q36E-200

Abstract: GS8342Q36E-250 GS8342Q36E-300
Contextual Info: Preliminary GS8342Q08/09/18/36E-300/250/200/167 36Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS832018GT-225I

Abstract: GS832036GT-250I 36T2 GS832018 GS832018T-166 GS832018T-200 GS832018T-225 GS832018T-250 GS832032 GS832036
Contextual Info: Preliminary GS832018/32/36T-250/225/200/166/150/133 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features cycles can be initiated with either ADSP or ADSC inputs. In

Contextual Info: K7P323674C K7P321874C 1Mx36 & 2Mx18 SRAM 36Mb Late Write SRAM Specification 119BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: M ay 1997 ^ÉL Micro Linear ML6026 36 Mbps Read Channel Filter/Equalizer GENERAL DESCRIPTION FEATURES The ML6026 is a monolithic analog filter/equalizer intended for hard disk drive read channel applications, capable of handling disk data rates up to 36Mbits/s, with

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: ADVANCE‡ 0.13µm Process 36Mb: 2 MEG x 18, 1 MEG x 32/36 PIPELINED ZBT SRAM 36Mb ZBT SRAM MT55L2MY18P, MT55V2MV18P, MT55L1MY32P, MT55V1MV32P, MT55L1MY36P, MT55V1MV36P 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O Features Figure 1: 100-Pin TQFP • High frequency and 100 percent bus utilization

BW35

Contextual Info: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDRIIb4 SRAM 36Mb DDRII CIO SRAM 4-WORD BURST MT57W4MH8J MT57W4MH9J MT57W2MH18J MT57W1MH36J FEATURES • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb2 SRAM 36Mb QDR SRAM 2-WORD BURST MT54V2MH18A MT54V1MH36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, Pipelined DDRb2 SRAM 36Mb DDR SRAM 2-Word Burst MT57V2MH18A MT57V1MH36A Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation

GS8320E18T-133

Abstract: GS8320E18T-150 GS8320E18T-166 GS8320E18T-200 GS8320E18T-225 GS8320E18T-250 GS8320E32T-150 GS8320E32T-166 GS8320E32T-200 GS8320E32T-225
Contextual Info: Preliminary GS8320E18/32/36T-xxxV 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features 250 MHz–133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address

29050 h

Abstract: IR 15015
Contextual Info: GS8321E18/32/36E-xxxV 250 MHz–133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 165-Bump FP-BGA Commercial Temp Industrial Temp Features Linear Burst Order LBO input. The Burst function need not be used. New addresses can be loaded on every cycle with no

GS8322ZV18

Abstract: GS8322ZV18B GS8322ZV72
Contextual Info: GS8322ZV18 B/E /GS8322ZV36(B/E)/GS8322ZV72(C) 119, 165 & 209 BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz–133 MHz 1.8 V VDD 1.8 V I/O Because it is a synchronous device, address, data inputs, and

Contextual Info: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

Contextual Info: Preliminary GS8342R08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS8322Z18/36A B/D -400/375/333/250/200/150 400 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 36Mb Pipelined and Flow Through Synchronous NBT SRAM 119 & 165 BGA Commercial Temp Industrial Temp Features Because it is a synchronous device, address, data inputs, and

GS8320Z36AGT-200I

Contextual Info: Preliminary GS8320Z18/36AGT-400/375/333/250/200/150 400 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 36Mb Pipelined and Flow Through Synchronous NBT SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features Because it is a synchronous device, address, data inputs, and

Contextual Info: Preliminary GS8342R08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS832218/36/72 B/E/C -xxxV 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs Features 250 MHz–133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the

Contextual Info: Product Preview GS8320ZV18/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM 250 MHz–133 MHz 1.8 V VDD 1.8 V I/O Features when the device is switched from read to write cycles. • NBT No Bus Turn Around functionality allows zero wait

burst generator

Contextual Info: Preliminary GS8320Z18/36AGT-400/375/333/250/200/150 400 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 36Mb Pipelined and Flow Through Synchronous NBT SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features Because it is a synchronous device, address, data inputs, and

GS8342DT10BGD-350I

Abstract: IR receiver TK 19 205
Contextual Info: GS8342DT07/10/19/37BD-450/400/350/333/300 36Mb SigmaQuad-II+TM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: Preliminary GS8342D08/09/18/36BD-400/350/333/300/250 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 36Mb SigmaQuad-IITM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaQuad Interface

Contextual Info: Product Preview GS832218 B/E /GS832236(B/E)/GS832272(C) 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features Flow Through/Pipeline Reads • FT pin for user-configurable flow through or pipeline operation