377S3320T1 Search Results
377S3320T1 Datasheets Context Search
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Contextual Info: Preliminary 377S3320T1 SDRAM MODULE 377S3320T1 SDRAM DIMM Intel 1.0 ver. Base 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung 377S3320T1 is a 32M bit x 72 Synchro |
OCR Scan |
KMM377S3320T1 KMM377S3320T1 32Mx72 32Mx4, 32Mx4 400mil 18bits 24-pin | |
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Contextual Info: SDRAM MODULE Preliminary 377S3320T1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. Revision 5 (November 1998) - Corrected DQ# at the input of SDRAM(D5) as DQ16-19 @Functional Block Diagram |
OCR Scan |
KMM377S3320T1 DQ16-19 KMM377S3320T1 32Mx72 32Mx4, 377S3320T1 44S32030T |