3P623 Search Results

marking code vey

Contextual Info: 3P623S00B/E Timing-Safe Peak EMI Reduction IC Safe™ clock. 3P623S00E accepts one reference input and drives out eight low-skew Timing-Safe™clocks. General Features Clock distribution with Timing-Safe™ Peak EMI Reduction 3P623S00B/E has an SS% that selects 2 different

Contextual Info: 3P623Z05A/B and 3P623Z09A/B Timing-Safe Peak EMI Reduction IC General Features Functional Description 3P623Z05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute Timing-Safe™ clocks with Peak EMI reduction. 3P623Z05 is an eight-pin version, accepts

ST TSSOP Marking

Contextual Info: 3P623S01B/C/J May 2007 rev 0.4 Timing-Safe Peak EMI reduction IC General Features • available in 8pin package. The 3P623S01J is the eight-pin version with crystal interface and accepts one • Clock distribution with Timing-Safe™ Peak EMI Reduction

Contextual Info: 3P623S00B/C/J/E/F/K May 2007 rev 0.4 Timing-Safe Peak EMI reduction IC General Features • 3P623S00B/C/J is the eight-pin version and accepts Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz • one reference input and drives out one low-skew clock.

Contextual Info: 3P623Z05A, 3P623Z05B, 3P623Z09A, 3P623Z09B Product Preview TIMING SAFEt Peak EMI Reduction IC http://onsemi.com Description 3P623Z05/09 is a versatile, 3.3 V Zero−delay buffer designed to distribute Timing−Safe clocks with Peak EMI reduction.

3P623

Abstract: 3P623S00BG ST TSSOP Marking
Contextual Info: 3P623S00A/B/C/D/E/F July 2005 rev 1.0 Zero Cycle Slip Peak EMI reduction IC General Features All parts have on-chip PLLs that lock to an input clock on ƒ Input frequency range: 20MHz - 50MHz. ƒ Zero input - output propagation delay. ƒ Low-skew outputs.

Contextual Info: 3P623S05/09A/B November 2006 rev 0.2 Zero Cycle Slip Peak EMI reduction IC General Features • 3P623S05A/B is the eight-pin version and accepts one reference input and drives out five low-skew clocks. • Clock distribution with Zero Cycle Slip™ Peak EMI

ST TSSOP Marking

Contextual Info: 3P623S01B/C/J March 2007 rev 0.3 Timing-Safe Peak EMI reduction IC General Features • available in 8pin package. The 3P623S01J is the eight-pin version with crystal interface and accepts one • Clock distribution with Timing-Safe™ Peak EMI Reduction

3I623S00BG

Abstract: IC 290 8pin
Contextual Info: 3P623S00A/B/C/D/E/F July 2005 rev 1.0 Zero Cycle Slip Peak EMI reduction IC General Features reference input and drives out one low-skew clock. ƒ 32 MHz Input frequency. ƒ Zero input - output propagation delay. ƒ Low-skew outputs. ƒ All parts have on-chip PLLs that lock to an input clock on

Contextual Info: 3P623S00B/C/J/E/F/K March 2007 rev 0.3 Timing-Safe Peak EMI reduction IC General Features • one reference input and drives out one low-skew clock. • Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz the CLKIN pin. The PLL feedback is on-chip and is

Contextual Info: 3P623S05/09A/B May 2007 rev 0.3 Timing-Safe Peak EMI reduction IC General Features • the eight-pin version and accepts one reference input and drives out five low-skew clocks. • Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz

ASM5P2305A

Contextual Info: 3P623Z05A/B 3P623Z09A/B May 2008 rev 0.1 Timing-Safe Peak EMI reduction IC designed to distribute Timing-Safe™ clocks with Peak EMI General Features • reduction. 3P623Z05 is an eight-pin version, accepts Clock distribution with Timing-Safe™ Peak EMI

3P623

Abstract: 3P623S00BG
Contextual Info: 3P623S00B/E May 2008 rev 0.5 Timing-Safe Peak EMI reduction IC Safe™ clock. 3P623S00E accepts one reference input General Features • and drives out eight low-skew Timing-Safe™clocks. Clock distribution with Timing-Safe™ Peak EMI Reduction