4 BIT ODD PARITY CHECKER Search Results

Contextual Info: M MOTOROLA M ilita ry 5 4 L S 2 8 0 9 -B it Odd/Even P arity G en erato r/C h ecker MPO uiliu ELECTRICALLY TESTED PER: MIL-M-38510/32901 The 54LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By

Contextual Info: M MOTOROLA M ilita ry 5 4 L S 2 8 0 9-B it Odd/Even P arity G en erato r/C h ecker MPO ELECTRICALLY TESTED PER: MIL-M-38510/32901 The 54LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By

Contextual Info: HITACHI/ L O G IC/ AR RA YS /M EN ^5 74 HC180 HD D Ë | 4 4 ^ 5 0 3 001 0425 O 92D 1 0 4 2 5 # 8-bit O dd/Even Parity G enerator/C hecker This universal, monolithic, 9-bit 8 data bits plus 1 parity bit parity generator/checker features odd/even outputs and

Contextual Info: GD54/74HC280, GD54/74HCT280 9-BIT EVEN/ODD PARITY GENERATOR/CHECKER General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 8 0 . They contain 9-bit inputs and 2 out­ puts even and odd parities to facilitate operation of Pin Configuration

Contextual Info: M M O T O R O L A SN54LS280 SN74LS280 D E S C R I P T I O N — The S N 5 4 L S / 7 4 L S 2 8 0 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded.

74180

Abstract: 74180 parity generator 4 bit even and odd parity checker 74180 parity 74180 bit 93180 8284 pin diagram 8284 ScansUX987
Contextual Info: TTL/MSI 93180/54180. 74180 8-BIT PARITY GENERATOR/CHECKER D E S C R IP T IO N — T h e 9 3 1 8 0 /5 4 1 8 0 or 7 4 1 8 0 are m ono lith ic, 8 -B it Parity Check/Generators which L O G IC S Y M B O L , feature control inputs and even/odd outputs to enhance operation in either odd or even parity

Contextual Info: 906ZWV Am2906 Quad Two-Input OC Bus Transceiver with Parity DISTINCTIVE CHARACTERISTICS • • • Internal 4-bit odd parity checker/generator. R eceiver has output latch for pipeline operation. R eceiver outputs sink 12 mA. Quad high-speed LSI bus transceiver.

4 bit odd parity checker

Abstract: 0539SA
Contextual Info: 906ZUIV Am2906 Quad Two-Input OC Bus Transceiver with Parity DISTINCTIVE CHARACTERISTICS • • • Internal 4-bit odd parity checker/generator. R eceiver has output latch for pipeline operation. R eceiver outputs sink 12 mA. Quad high-speed LSI bus transceiver.

t1128

Contextual Info: 54ACT11280,74ACT11280 9-BIT PARITY GENERATORS/CHECKERS S C A S 0 4 6 A - D3148, A U G U S T 1988 - RE V IS E D A P R IL 1993 • * Inputs Are TTL-Voltage Compatible ■ I * Generates Either Odd or Even Parity for Nine Data Unes I I * Cascadable for n-Bits Parity

PFA 10Z

Abstract: 54ACT 74ACT11286 D3166 54ACT11286
Contextual Info: 54ACT11286, 74ACT11286 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORTS TI0124— D3166, AU G U ST 1986— REVISED M AR CH 1990 Inputs are TTL-Voltage Compatible 5 4 A C T 1 1286 . . . J P A C K A G E 74A C T11286 . . . D OR N PACKAGE Generates Either Odd or Even Parity for

Parity Generators

Abstract: SN74 SN74ALS280 SN74AS280 SV10 cs86 I80-S
Contextual Info: SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982-R E V IS E D M AY 1986 Generates Either Odd or Even Parity for Nine Data Lines S N 7 4A L S 2 80 , S N 7 4 A S 2 8 0 . . . D O R N PACKAGE TO P V IE W Cascadabie for n-Blts Parity

Contextual Info: SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982 - REVISED MAY 1986 Generates Either Odd or Even Parity for Nine Data Lines SN 74A LS280, S N 7 4 A S 2 S 0 . . . D O R N PA CKAG E T O P V IE W Cascadable for n-Bits Parity G [ 1T J Ü D V C C

54HC280

Contextual Info: S N 54H C 280, SN74HC2B0 9 BIT ODDIEVEN PARITY GENERATORSfCHECKERS D 2 6 6 4 , DECEMBER I 9 8 2 -R E V IS E D JUNE 19B9 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits • Can Be Used to Upgrade Existing Systems Using MSI Parity Circuits

AM2906PC

Abstract: AM2906DC AM2906DC-B AM2906DM AM2906DM-B AM2906FM AM2906FM-B AM2906XC AM2906XM P-24
Contextual Info: Am2906 Quad Two-Input OC Bus Transceiver With Parity Distinctive Characteristics • Quad high-speed LSI bus transceiver. • Open-collector bus driver. • Two-port input to D-type register on driver. • Bus driver output can sink 100 mA at 0.8 V max. • Internal odd 4-bit parity checker/generator.

X20C

Contextual Info: 54AC 11286, 74AC11286 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORTS T I0 1 19— D 3165, AUGUST 1988— REVISED MARCH 1990 • Generates Either Odd or Even Parity for Nine Data Lines 5 4 A C 1 1286 . . . J P A C K A G E 7 4 A C 11 2 86 . . . 0 O R N P A C K A G E

Contextual Info: F10160 • F10560 12-BIT PARITY CHECKER/GENERATOR DESCRIPTION — The F10160 and F10560 are 12-Input Parity Generators. The output w ill be HIGH when an odd number of inputs are HIGH; typical delay is 4 ns. For applications requiring fewer than 12 inputs, unused inputs may be left open, since

Contextual Info: SN74LS280N IL00 * TTL 9-BIT ODD / EVEN PARITY GENERATOR / CHECKER -TOP VIEW8 D7 DATA 7 IN 1 VCC(+5V) 14 9 10 D8(DATA 8) IN 2 13 D6(DATA 6) IN 11 12 3 NC 12 D5(DATA 5) IN 13 1 D9(DATA 9) IN 4 11 D4(DATA 4) IN 2 4 EV(EVEN)OUT 5 10 D3(DATA 3) IN OD(ODD)OUT

amd 2907

Abstract: amd 2908
Contextual Info: 806ZU1V/Z06ZUIV Am2907/Am2908 Quad Bus Transceivers with Interface Logic DISTINCTIVE CHARACTERISTICS Quad high-speed LSI bus-transceiver D-type driver register with open-collector bus driver output can sink 100mA at O.BV max. Internal 4-bit odd parity checker/generator

interlace parity

Abstract: application of parity checker/generator i2 bus latch
Contextual Info: Am2917A Am2917A Quad Three-State Bus Transceiver with Interface Logic DISTINCTIVE CHARACTERISTICS Quad high-speed LSI bus-transceiver D-type driver register with tri-state bus driver output can sink 48mA at 0.5V max. Internal 4-bit odd parity checker/generator

Contextual Info: Ü7E D I b¡E!4l iñ27 D Q m i T q MITSUBISHI ADVANCED SCHOTTKY TTL , M 7 4 F 2 80P /FP /D P MITSUBISHI -CDGTL LOGIC} 07E D r 9 -B IT ODD/EVEN PARITY GENERATOR/CHECKER 7 DESCRIPTION The M74F280P is a semiconductor integrated circuit containing a 9-bit parity generator/checker.

SN74F286

Contextual Info: SN54F286, SN74F2B6 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORT D 29 32, M A R C H 1 9 8 7 -R E V IS E D J A N U A R Y 1989 SN 54F286 . . . J PACKAGE S N 7 4 F 2 8 6 . . . D OR N P A C K A G E • Generates Either Odd or Even Parity for

4 bit odd parity checker

Abstract: 4-bit even parity checker circuit diagram AM2916 AM-16A
Contextual Info: Am2916A Am2916A Quad Three-State Bus Transceiver with Interface Logic DISTINCTIVE CHARACTERISTICS • • • • Internal 4 -bit odd parity checker/generator • R eceiver output latch can sink 12mA at 0.5V •3.5V minimum output high voltage for direct interface to

4 bit odd parity checker

Abstract: interlace parity
Contextual Info: i Am2917A E < Quad Three-State Bus Transceiver with Interface Logic DISTINCTIVE CHARACTERISTICS Quad high-speed LSI bus-transceiver D-type driver register with tri-state bus driver output can sink 48mA at 0.5V max. Internal 4-bit odd parity checker/generator

74AS280

Contextual Info: TYPES SN54AS280, SN74AS280 9 BIT PARITY GENERATORS/CHECKERS D 2 6 6 1 , DECEMBER 1 9 8 2 -R E V IS E D DECEMBER 1 9 8 3 Generates Either Odd or Even Parity for Nine Data Lines S N 5 4 A S 2 8 0 . . . J PACKAGE S N 7 4 A S 2 8 0 . . . N PACKAGE {TOP VIEW •