4 INPUT D FLIP FLOP Search Results

74LVC1G175

Abstract: 74LVC1G175GF 74LVC1G175GM 74LVC1G175GV 74LVC1G175GW 74LVC1G175GS
Contextual Info: 74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Rev. 4 — 4 October 2010 Product data sheet 1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data D input, clock (CP) input, master reset (MR) input, and Q

Contextual Info: 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 4 — 24 November 2011 Product data sheet 1. General description The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data D input, clock (CP) input, master reset (MR) input, and Q

Contextual Info: Semiconductor May 1995 5 4 F /7 4 F 3 7 7 O ctal D Flip-Flop w ith Clock Enable General Description Features The ’F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the

MC74AC273

Abstract: MC74AC373
Contextual Info: MOTOROLA M C74AC377 MC7 4 A C T377 O ctal D Flip-Flop w ith C lock Enable OCTAL D FLIP-FLOP WITH CLOCK ENABLE The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads

iC4013BP

Contextual Info: TC4013BP/BF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC IC4013BP/TC4013BF DUAL D-TYPE FLIP FLOP T C 4 0 1 3 B P / B F contains two independent circuits of D type flip-flop. The input level applie'd to D A TA input are transferred to Q and Q" output by r is­

Contextual Info: 74AUP1G374 Low-power D-type flip-flop; positive-edge trigger; 3-state Rev. 7 — 4 July 2012 Product data sheet 1. General description The 74AUP1G374 provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input D that meet the set-up and hold times requirements on the

74HC74

Abstract: 74ls74 timing setup hold 74hc74 pin diagram 74LS74 PINOUT 74HC74 pin configuration 74hct74 Current 74HCT74 TTL 74hc74 74HC GD74HCT74
Contextual Info: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 4 . They consist of two D-type flip-flops with individual preset, clear, and clock inputs. Infor­ mation at a D-input is transferred to the correspon­

74LS175P

Abstract: 74LS17 qi 20pin M74LS175P
Contextual Info: MITSUBISHI LSTTLs M 74LS175P QUADRUPLE D -TY P E FLIP FLOP W IT H RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74L S 17 5P is a semiconductor integrated circuit containing 4 positive edge-triggered D -type flip-flops w ith common clock input T and direct reset input R q and

ic 74 hc 10

Contextual Info: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 4 . They consist of two D-type flip-flops with individual preset, clear, and clock inputs. Infor­ mation at a D-input is transferred to the correspon­

74HC273

Abstract: 54HC273
Contextual Info: SN54HC273, SN74HC273 OCTAL D TYPE FLIP-FLOPS WITH CLEAR D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1 9 8 7 Contains Eight Flip-Flops with Single-Rail Outputs T O P V IE W • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers

74HC273

Abstract: 54HC273 VJ20 SM74HC273
Contextual Info: SN54HC273, SN74HC273 OCTAL D TYPE FLIP-FLOPS WITH CLEAR D 2 6 8 4 , DECEMBER 1 9 8 2 - REVISED JUNE 19B9 Contains Eight Flip-Fiops with Single-Rail Outputs SN 54H C273 . . . J PACKAGE SN74HC273 . DW OR N PACKAGE ITOP VIEW CLR n • Individual Data Input to Each Flip-Flop

M74LS175P

Abstract: 12 V T flip flop IC 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS175P QUADRUPLE D -TY P E FLIP FLOP W IT H RESET DESCRIPTION The M 74L S 17 5P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 4 positive edge-triggered D -type flip-flops w ith common clock input T and direct reset input R q and

Contextual Info: HITACHI/ LOGIC/ARRAYS/ IEM 4 ^ 5 0 3 IE 92D - HD7 4 HC174 # DOlDWai 3 10421 T-46-07-1Û D Hex D-type Flip-Flops (with Clear) This device contains 6 master-slave flip-flops with a common • PIN ARRANGEMENT clock and common dear. Data on the D input having the

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 4 TC407 6 B P 7 6 B P 4 -BIT D-TYPE REGISTER TC4076BP is the register which consists of four D type flip-flops having 3-stage outputs, and these four flip-flops are controlled by common CLOCK input and

Contextual Info: HD74HC17 4 • Hex D-type Flip-Flops This device contains 6 master-slave flip-flops with a common with Clear PIN ARRANGEMENT clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM HE HD74HC273 # DËJ 44Tb2Q3 QQIQHTt. Octal D-type Flip-Flops with Clear 92D This device contains 8 master-slave flip-flops with a common d o c k and common clear. Data on the D input having the | 10476 D T -4 6 -0 7 -1 1 PIN ARRANGEMENT

Contextual Info: GD54/74HC175, GD54/74HCT175 QUAD D-TYPE FLIP-FLIPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 7 5 . They contain four D-type flip-flops with common clock and clear inputs, and separate data inputs. Information at a data input is

Contextual Info: 5 4 A C /7 4 A C 3 7 7 • 54 A C T /7 4 A C T 3 7 7 O ctal D Flip-Flop w ith Clock Enable General Description Features The ’A C /’AC T377 has eight edge-triggered, D -type flip-flo p s w ith individual D inputs and Q outputs. The com m on b u ff­ ered C lock CP input loads all flip-flo p s sim ultaneously,

Contextual Info: 74LVC821A 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Rev. 4 — 23 November 2012 Product data sheet 1. General description The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input pin CP and an

Contextual Info: 74LVCH162374A 16-bit edge-triggered D-type flip-flop with 30  series termination resistors; 5 V input/output tolerant; 3-state Rev. 4 — 22 January 2013 Product data sheet 1. General description The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs

Contextual Info: 40175B/74C175/54C175 QUAD D FLIP-FLOP DESCRIPTION — The 4 0 1 7 5 B is a Quad Edge-Triggered D Flip-Flop with four Data Inputs D q-D3 , a Clock Input (CP) an overriding asynchronous Master Reset (MR), four Buffered Outputs (Q0-Q3) and four Complementary Buffered Outputs (Q0-Q3).

14521B

Abstract: HD14521
Contextual Info: H D 14521B 2 4 - S tage Frequency Divider The HD 1452IB consists o f a chain o f 24 flip-flops with an input circuit that allows three m odes o f operation. The input will function as a crystal oscillator, an RC oscillator, or as an input buffer for an external oscillator. Each flip-flop divides the frequency o f the

Contextual Info: S ANYO SEMICONDUCTOR CORP 12 E D I 0002751 3 T - 4 ^ 0 7 - 1 C M O S High-Speed Standard Logic LC74HC Senes 3021B Octal 3-State Noninverting D-Type Flip-Flop £*2078 Features The LC74HC374 consists of 8 identical noninverting D-type flip-flops with 3-statfcoutputs. The clock input CLK)

dm8551

Abstract: cd06060 74173 pin configuration
Contextual Info: Signetics 7 4 1 7 3 , LS1 7 3 Flip-Flops Quad D-Type Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • Edge-triggered D-type register • Gated Input enable for hold "do nothing" mode • 3-State output buffers • Gated output enable control