74HC273 Search Results

Contextual Info: Technical Data CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering ■ Buffered inputs ■ Typical fmat — 60 MHz @ Vcc ~ 5 V, C l = 15pF, 7a = 25° C

74hc273

Abstract: harris hct273
Contextual Info: [ /Title CD74 HC273 , CD74 HCT27 3 /Subject (High Speed CMOS Logic Octal DType Flip- CD54/74HC273, CD54/74HCT273 Data sheet acquired from Harris Semiconductor SCHS174A High Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2000

74HC273

Abstract: 74HCT273
Contextual Info: G E SOLI» STATE 01 D E | 3Û7S0Ô1 001175=1 4 Technical Data. T-46-07-05 CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering

74hc273a

Abstract: 74HC273
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA O ctal D Flip-Flop w ith Common Clock and Reset M C54/74HC273A High-Performance Silicon-Gate CMOS J SUFFIX CERAMIC PACKAGE CASE 732-03 The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

74hc273a

Abstract: 74hc273 ls273
Contextual Info: MOTOROLA SC LOGIC m blE V b3b?2S2 GD'U'U? 643 M M O T M MOTOROLA / " V ó - o 7 _ // SEMICONDUCTOR! TECHNICAL DATA MC54/74HC273A Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The MC54/74HC273A is identical in pinout to the LS273. The device inputs

C273A

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop w ith Common Clock and Reset MC54/74HC273A High-Performance Silicon-Gate CMOS The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

Contextual Info: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave D- Pin Configuration type flip-flops with a common Clock and common

74hc273

Abstract: 803E-9 LS273
Contextual Info: M O T O R O L A SC { L O G I C } OS D "Jti3L>7ES5 D0-ûD3fl]i □ T -V 6-Û7 -OS MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC273 O ctal D Flip-Flop w ith Com m on C lock and Reset High-Perform ance Silicon-G ate C M O S T h e M C 5 4 /7 4 H C 2 7 3 is identical in pinout to the LS273. T h e device inputs are

74HC273

Abstract: 74hct273 74LS273 74HC GD74HC273 pin diagram of 74ls273 GD74HC27 OT273
Contextual Info: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave D- Pin Configuration type flip-flops with a common Clock and common

74HC273

Abstract: 74hct273
Contextual Info: [ /Title CD74 HC273 , CD74 HCT27 3 /Subject (High Speed CMOS Logic Octal DType Flip- CD54/74HC273, CD54/74HCT273 Data sheet acquired from Harris Semiconductor SCHS174A High Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2000

74hc273

Abstract: 54HC273 74HCT273
Contextual Info: Technical Data, CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Comm on clock and asynchronous master reset • Positive-edge triggering ■ Buffered inputs ■ Typical fm,K = 60 M H z 'SET

74HC273

Abstract: HCT273 74HC273N TSSOP20 Package 74HCT273 SO20 Package SSOP20 package 74HC273BQ 74HC273D 74HC273DB
Contextual Info: 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 24 January 2006 Product data sheet 1. General description The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL .

74hc273a

Abstract: 74HC273 MC54/74HC273A LS273 MC54HCXXXAJ MC74HCXXXAN MC54-74HC273A
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA O ctal D Flip-Flop w ith Common Clock and Reset MC54/74HC273A High-Performance Silicon-Gate CMOS J SUFFIX CERAMIC PACKAGE CASE 7 3 2 -0 3 The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M 74HC273P M 74HC273DW P OCTAL D -T Y P E F L IP -F L O P W ITH COMMON CLOCK AND R ESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74H C 273 is a sem iconductor integrated circuit con­ sisting of eigh t p o s itiv e -e d g e trig g e re d D -type flip flops

74hc273

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC273 O ctal D Flip-Flop w ith Common C lo ck and Reset High-Performance Silicon-Gate CMOS The M C 54/74H C 27 3 is id entical in p in o u t to the LS273. The device in p u ts are co m p a tib le w ith standard CM O S o u tp u ts ; w ith pullu p resistors, th e y are c o m p a tib le

74HC273A

Abstract: 74HC273 DL129 LS273 MC54HCXXXAJ MC74HCXXXAN
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset MC54/74HC273A High–Performance Silicon–Gate CMOS The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

Contextual Info: 74HC273-Q100; 74HCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger Rev. 1 — 19 June 2013 Product data sheet 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock CP and master reset (MR) inputs. The outputs Qn assume the

74hc273

Abstract: 74HCT273
Contextual Info: Technical Data CD54/74HC273 CD54/74HCT273 File Number 1 4 7 9 .1 High-Speed CMOS Logic Octal D Flip-Flop with Reset CLOCK CP “ D 2- -QO - 01 -02 03- -0 3 00□I - DATA _ IN P U T S 04- -0 4 05- -0 5 06- -0 6 07- -0 7 RESET TTR _ OATA O U TP U TS Type Feature*:

74HC273A

Abstract: 74HC273 DL129 LS273 MC54HCXXXAJ MC74HCXXXAN MC54-74HC273A D4714
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset MC54/74HC273A High–Performance Silicon–Gate CMOS The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

74HC273

Abstract: 74LS273 74hct273 74HC GD54HC273 GD74HC273 GD54-74HC
Contextual Info: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description Pin Configuration These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave Dtype flip-flops with a common Clock and common

74HC273

Abstract: 74hct273 CD54HC273 CD54HCT273 CD74HC273 CD74HCT273
Contextual Info: T -H & -c r7 -*// Technical Data CD54/74HC273 CD54/74HCT273 Filé Number HARRIS SEMICOND SECTOR 27E » m 1479 43G2271 001774^ S Si HAS High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering

74HC273

Abstract: 74HC273D 74HCT273 74HC273BQ 74HC273DB 74HC273N 74HC273PW DIP20 74HCT273D
Contextual Info: 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Product data sheet 1. General description The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC273; 74HCT273 has eight edge-triggered, D-type flip-flops with individual

74hc273

Abstract: HCT273 74hct273 74HC273D
Contextual Info: 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 4 — 10 June 2013 Product data sheet 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock CP and master reset (MR) inputs. The outputs Qn will assume the state of

74hc273

Abstract: tc741
Contextual Info: TC74LVQ273F/FW/FS OCTAL D-TYPE FLIP FLOP WITH CLEAR The TC74LVQ273 is a high speed CMOS OCTAL D-FLIP FLOP fabricated w ith silicon gate and double-layer metal w iring C2M OS technology. Designed for use in 3.3 Volt systems, it achieves high speed operation w hile maintaining the CMOS low power