462L17S Search Results

Contextual Info: P W iy iM D K M W in tJ . 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH "See Table 1 for Proliferation Options High Performance CHMOS EPROM 5 Interrupt Sources 24 MHz Operation Programmable Serial Port

132-Lead

Abstract: AD30/ako 451 960
Contextual Info: A E W Â N l ! DKIIF ß}[ü iflA 70® ß !0 in te l 80960J A /JF EMBEDDED 32-BIT MICROPROCESSOR High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers

LB L293-N1N2-45-1-10-R18-Z-XX

Contextual Info: 4-MBIT 256K X 16, 512K X 8 BOOT BLOCK FLASH MEMORY FAMILY 28F400BX-T/B, 28F004BX-T/B • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read — 60/80/120 ns Maximum Access Time

Contextual Info: p rc g y B M M ft? 8XC52/54/58 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C52/80C52/80C32/87C54/80C54/87C58/80C58 •See Table 1 for Proliferation Options • 6 Interrupt Sources ■ High Performance CHMOS EPROM/ ROM/CPU ■ Programmable Serial Channel with:

diodo sl r7

Abstract: TMs 1122 NL BC 1305 pin outs DIODO 6N c11 cpl 100 39p HBT 01 - 04G Intel486TM PROCESSOR FAMILY 6M91 INTEL I486 DX2 diodo s4 6n
Contextual Info: intei MILITARY ln t e l 486 TM PROCESSOR FAMILY • lntelDX4TM Processor — Up to 100-MHz Operation -S peed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

UCS 1212

Abstract: 272072 ucs 1212 1226 8086 ic tester circuit diagram 272332 KU80C186EC20
Contextual Info: p fö n y B ä n n iO A R R f in te i 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS H Fully Static Operation • True CMOS Inputs and Outputs ■ Integrated Feature Set: — Low-Power, Static, Enhanced 8086 CPU Core — Two Independent DMA Supported

Contextual Info: in te i 87C51FA/87C51FB/87C51FC/87C51FC-20 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Automotive FX Core Architecture Device • Quick Pulse Programming Algorithm Extended Automotive Temperature Range -4 0 °C to + 125°C Ambient ■ ■ ■ ■ Available In 12 MHz, 16 MHz and

01ag

Abstract: ML616
Contextual Info: in te l CHAPTER 3 INSTRUCTION SET REFERENCE This chapter describes the complete Intel Architecture instruction set, including the integer, floating-point, MMX technology, and system instructions. The instruction descriptions are arranged in alphabetical order. For each instruction, the forms are given for each operand combi­

Bck 2801

Abstract: intel i486dx i486 sx i82596CA gus manual 10BASE2 10BASE5 80960CA 82596CA I487
Contextual Info: 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Perform s Com plete C SM A /C D Medium Access Control MAC Functions— Independently o f CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T,

intel i486dx

Abstract: lpk 12-23 PQFP 132 PACKAGE DIMENSION intel 10Broad36 80960KB Programmer Reference manual 10BASE2 10BASE5 80960CA 82596CA Bck 2801
Contextual Info: 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Perform s Com plete C SM A /C D Medium Access Control MAC Functions— Independently o f CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T,

Contextual Info: 80C196KB10/83C196KB10/80C196KB12/83C196KB12 PACKAGING The 80C196KB is available in a 68-pin PLCC package, an 80-pin QFP package and a 68-pin PGA package. Contact your local sales office to determine the exact ordering code for the part desired. Package Designators: N = 68-pin PLCC, S = 80-pin QFP and A = 68-pin PGA.

scr tic 1160

Abstract: Cote Micro Technique 01BS2
Contextual Info: in t é l 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

Contextual Info: PRELIMINARY in te i INTEL 430MX PCISET 82371 MX MOBILE PCI I/O IDE XCELERATOR MPIIX • Provides a Bridge Between the PCI Bus and Extended I/O Bus — PCI Bus; 25-33 MHz — Extended I/O Bus; 7.5-8.33 MHz ■ System Power Management (Intel SMM Support) — Programmable System Management