512X256X8 Search Results

TC528257

Abstract: n724
Contextual Info: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The

SF229

Abstract: toshiba s105
Contextual Info: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2M b it C M O S m u ltip o rt m e m o ry eq u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m a ccess m e m o ry R A M p o rt a n d a 5 1 2 -w o rd s by

TC518129

Abstract: de interlace
Contextual Info: TOSHIBA TC518129AP/ASP/AF/AFW-80/10/12 TC518129APL/ASPL/AFL/AFWL30/10/12 TC518129AFTLS0/10/12 SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description The T C 5 1 8 1 2 9 A is a 1M bit high speed C M O S p se udo static R AM organized as 131,07 2 w o rd s by 8 bits. The TC 5 18 1 29A utilizes

518128

Abstract: 518128apl TC518128
Contextual Info: TOSHIBA TC518128APL/AFL/AFWL-80LV/10LV/12LV TC518128AFTLS0LV/10LV/12LV SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description T h e T C 5 1 8 1 2 8 A -L V is a 1M bit high speed C M O S p se udo static R AM organized as 131,07 2 w o rd s b y 8 bits. The T C 5 1 8 1 2 8 A -L V

TC518129AFwl

Contextual Info: TOSHIBA TC518129APL/AFL/AFWL-80LV/lOLV/12LV TC518129AFTL80LV/lOLV/12LV SILICON GATE CM O S 131,072 W ORD x 8 BIT C M O S PSEUDO STATIC RAM D escription The TC5181 29A-LV is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129A-LV

Contextual Info: High Performance 128Kx8 C M O S SRAM p i AS7C1024 AS7C1024L 128Kx8 CM O S S RAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE1, CE2, OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: March 1994 PRELIMINARY DATA SHEET_ M 65608 128 K x 8 ULTIMATE CMOS SRAM FEATURES . ACCESS TIME: COMMERCIAL: 25/30/35/45 ns INDUSTRIAL AND MILITARY: 25 * /30/35/45 ns . VERY LOW POWER CONSUMPTION ACTIVE: 250 mW (typ) STANDBY: 1 pW (typ)

Contextual Info: TC518129CPL/CFWL/CFIL-70/80/10 TC518129CPL/CFWL/CFIL-70L/80L/10L SILICON GATE CMOS P R E L IM IN A R Y 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM D e s c rip tio n The T C 5 1 8 1 2 9 C is a 1 M bit high speed C M O S pse udo static RAM organized as 131,072 w o rd s by 8 bits. T h e T C 5 1 8 1 2 9 C utilizes

Contextual Info: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2 M b it C M O S m u ltip o rt m e m o ry e q u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m access m e m o ry R A M p o rt an d a 5 1 2 -w o rd s b y

st d83

Abstract: TC518128C d83 st
Contextual Info: TOSHIBA TC518128CPL/CSPL/CFL/CFWL/CFIL-70/80/10 TC518128CPL/CSPL/CFL/CFWL/CFIL-70L/80L/10L PRELIMINARY SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description T h e T C 5 1 8 1 2 8 C is a 1M bit high speed C M O S pse udo static RAM organized as 131,07 2 w o rd s by 8 bits. The TC 5 18 1 28C utilizes

Contextual Info: fax id: 1047 CY7C109 CY7C1009 ^C YPR ESS 128K x 8 Static RAM active HIGH chip enable CE 2 , an active LOW output enable (OE), and three-state drivers. Writing to the device is accom plished by taking chip enable one (CE-|) and write enable (WE) inputs LOW and chip enable two (CE 2 ) input HIGH. Data on

Contextual Info: <ä v GM76C8128A/AL/ALL GoldStar 131,072 WORDS x 8 BIT CMOS STATIC RAM GOLDSTAR ELECTRON CO., LTD. Pin Configuration Description The GM76C8128A/AL/ALL is a 1,084,576 bits stat­ ic random access memory organized as 131,072 words by 8 bits. Using a 0.8um advanced CMOS

Contextual Info: KM658128/L/L-L/LD/LD-L Pseudo SRAM SAMSUNG ELECTRONICS INC 42E D BB 7 ^ 4 1 4 2 12 8K X 8 Bit CMOS Pseudo Static RAM . QQiaflSS T f FEATURES GENERAL DESCRIPTION • Fast Access Time: — 5 1 Access Time . 80,100,120ns Max. — Cycle Time . Random Read/Write Cycle

tc528257

Abstract: W640 SFC39 DIN 41162
Contextual Info: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS m ultiport m em ory equipped with a 262,144-words by 8 -bits dynam ic random access mem ory RAM port and a 512-words by 8 -bits static serial access memory (SA M ) port. The

SOJ32-P-400-1

Abstract: TC55V8128BJ 512X256X8
Contextual Info: TOSHIBA TC55V8128BJ/BFT-8 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The TC55V8128BJ/BFT is a 1,048,576 bits high speed static random access memory organized as 131,072 words by 8 bits using CMOS technology, and operated from a single 3.3V supply. Toshiba’s

MA1019

Contextual Info: October 2001 Advance Information AS7C1025A AS7C31025A 5V/3.3V 128K X 8 CMOS SRAM Revolutionary pinout Features • • • • • AS7C1025A (5V version) AS7C31025A (3.3V version) Industrial and commercial temperatures Organization: 131,072 x 8 bits High speed

Contextual Info: $SULO##5333 $6:&4357 $6:&64357 8926169#45;.ð;#&026#65$0#+ YROXWLRQDU\#3LQRXW, HDWXUHV • AS7C1024 (5V version) • AS7C31024 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time

AS7C31024-12TC

Abstract: AS7C1024-15TJC
Contextual Info:  $6& $6& .ð&02665$0 &RPPRQ,2 IDPLO\ HDWXUHV • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 64Kx8) - 400 mil SOJ - 8mm × 20mm TSOP • ESD protection ≥ 2000 volts

Contextual Info: March 2001 Advance Information AS7C1025A AS7C31025A 5V/3.3V 128K X 8 CMOS SRAM Revolutionary pinout • • • • • • Latest 6T 0.25u CMOS technology 2.0V data retention Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O

megatron

Abstract: 10N12 Beacon 406 MHz AS7C31024 BJ 919 26A41
Contextual Info: High Performance 128Kx8 3.3V CMOS SRAM H J 8 |j ^ AS7C31024 AS7C31024L PRELIMINARY _ Low Voltage 128Kx8 CMOS SRAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • Single 3.3 ±0.3V power supply

7C1025-15

Abstract: 20013 AS7C1025 AS7C31025 ASC310 275mWmax 7C1025
Contextual Info: H ig h P erfo rm a n ce 128K x8 CMOS SRAM » A S7C 1 025 A S 7 C 3 102 5 H A 1 2 8 K X 8 CM O S SRAM C o m m o n I / O • T T L - c o m p a tib le , th r e e - s ta te I / O • H ig h s p e e d • 3 2 - p i n JEDEC s ta n d a r d p a c k a g e - 3 0 0 / 4 0 0 m i l SOJ

Contextual Info: M O S E L V /TE LiC V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM 70 80 10 Max. RAS Access Time, tHAC HIGH PERFORMANCE V52C812B 70 ns 80 ns 100 ns Max. CAS Access Time, Ocac ) 20 ns 25 ns 25 ns Max. Column Address Access Time, (t*) 35 ns

V52C8128

Abstract: V52C8128-80
Contextual Info: MOSEL- VITELIC V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM HIGH PERFORMANCE V52C8128 70 PRELIMINARY 80 10 Max. RAS Access Time, tRAc 70 ns 80 ns 100 ns Max. CAS Access Time, (tcAc) 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t ^ )

km658128

Abstract: 658128 PSEUDO SRAM
Contextual Info: KM658128/L/L-L/LD/LD-L Pseudo SRAM 12 8 K X 8 Bit CMOS Pseudo Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time: — CE Access Time . 80,100,120ns Max. — Cycle Time . Random ReadfWrite Cycle Time . 130,160,190ns (Max.) • Low Power Dissipation . 200mW typ. (Active)