54AC11 Search Results

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

74AC11827

Contextual Info: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

Contextual Info: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to

Contextual Info: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

74AC11873

Contextual Info: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB

74AC11533

Abstract: 123D20
Contextual Info: *»4AP11*511 744011*511 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0085— D2957, JULY 1987— REVISED JAN U AR Y 1990 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE • 8-Latches in a Single Package • 3-State Bus-Driving Inverting Outputs

74AC108

Abstract: so 54 t 74AC11066
Contextual Info: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to

Contextual Info: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout

Contextual Info: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process

TH 2267

Abstract: 74AC11191
Contextual Info: 54AC11191, 74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS TI0151— D3426, MARCH 1990 • Single Down/Up Count Control Line 54AC11191 . . . J PACKAGE 74AC11191 . . . DW OR N PACKAGE • Look-Ahead Circuitry Enhances Speed of Cascaded Counters TOP VIEW

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Contextual Info: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D3103. APRIL 1988 - REVISED APRIL 1993 * * * * * * * * Designed Specifically for High-Speed Memory Decoders and Data Transmission

74AC11533

Contextual Info: 54AC11533, 74AC11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE 8-Latches in a Single Package

Contextual Info: 54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES TI0056— D2957, JULY 1987—REVISED MARCH 1990 54AC11027 . . . J PACKAGE 74AC11027 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pln V c c and GND Configurations to

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D 2957, JULY 1987 - R EVISED APRIL 1993 * Flow-Through Architecture Optimizes PCB Layout 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11175, 74AC11175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR T 10109— D3388, DECEMBER 1989— REVISED MARCH 1990 • Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators 5 4 A C 11 1 75 . . . J P A C K A G E 74A C 11175 . . . DW O R N PACKAGE