TI018 Search Results

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [

AUO-PL321.15

Abstract: 54AC11181 74AC 74AC11181
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TI0184— D3119, APRIL 1989— REVISED MARCH 1990 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE Flow-Through Architecture to Optimize PCB Layout TOP VIEW Minimize High-Speed Switching Noise

54AC16244

Abstract: 74AC16244
Contextual Info: 54AC16244, 74AC16244 16-BIT BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0180— D3465, M ARCH 1980 Member of the Texas Instruments Wldebus Family 54AC16244 . . . W D PACKAGE 74AC16244 . . . DL PACKAGE TOP VIEW Packaged In Shrink Small Outline 300-mil

74ACT11181

Contextual Info: I 31E D TEXAS INSTR LOGIC • ^(31723 DQflflbS? fi ■ T I I 3 54ACT11181, 74ACT11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T-MQ-I/-00 TI0183— D3200, OCTO BER 1989—REVISED M AR C H 1990- 54ACT11fS1 . . . JT PACKAGE 74A C T 11181 . . . DW O R NT PACKAGE

74ACT11181

Abstract: D3200
Contextual Info: 54ACT11181, 74ACT11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TI0183— D 3200, OCTOBER 1989— REVISED MARCH 1990 • Inputs are TTL-Vollage Compatible 54ACT11181 . . . JT PACKAGE 74ACT11181 . . . DW OR NT PACKAGE Flow-Through Architecture to Optimize PCB

74ACT11086

Abstract: 4bti
Contextual Info: 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0185— D3390, NOVEM BER 1989 • Inputs are TTL-Voltage Compatible 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB Layout TOP VIEW 1A[ 1 Y[

t1188

Contextual Info: 54AC11881, 74AC11881 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TI0187— 0 3 4 7 9 , MARCH 1990 Full Look-Ahead for High-Speed Operations on Long Words 54AC11681 . . . JT PACKAGE 74AC11881 . . . OW OR NT PACKAGE TOP VIEW Arithmetic Operating Modes: Addition,

Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TI0184— D3119, APRIL 1989—REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Center-Pin Vq c and GND Configurations to

ACT16244

Abstract: 74ACT16244
Contextual Info: 54ACT16244, 74ACT16244 16-BIT BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0181— D3465. MARCH 1990— REVISED JULY 1990 54ACT 16244 . . . WD PACKAGE 74ACT16244 . . . DL PACKAGE Members of the Texas Instruments Widebus Family TOP VIEW Packaged in Shrink Small Outline 300-mil

74ACT11377

Abstract: D3450
Contextual Info: 54ACT11377, 74ACT11377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0186— D3450, M ARCH 1990 54ACT11377 . . . JT PACKAGE 74ACT11377 . . . DW Or NT PACKAGE Inputs are TTL-Voltage Compatible Contains Eight D-Type Flip-Flops TOP VIEW Clock Enable Latched to Avoid False

74ACT11181

Contextual Info: 54ACT11181, 74ACT11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TI0183— D3200, OCTOBER 1989— REVISED MARCH 1990 54ACT11181 . . . JT PACKAGE 74ACT11181 . . . DW OR NT PACKAGE • Inputs are TTL-VoKage Compatible Flow-Through Architecture to Optimize PCB

AUO-PL321.15

Abstract: 54AC11181 74AC 74AC11181 AC11881 hlab D3119
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TI0184— D3119, APRIL 1989— REVISED MARCH 1990 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE Flow-Through Architecture to Optimize PCB Layout TOP VIEW Minimize High-Speed Switching Noise

Contextual Info: 54ACT16244, 74ACT16244 16-BIT BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0181— 0 3 4 6 5 . MARCH 1990 54ACT16244 . . . WD PACKAGE 74ACT16244 . . . DL PACKAGE Member of the Texas Instruments Widebus” Family TOP VIEW Packaged in Shrink Small Outline 300-mll

Contextual Info: 54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0189— 0 3 4 7 7 , M AHCH 1990 Member of the Texas Instruments Wldebus Family 54A C 16646 74A C 16646 WP PACKAGE DL PACKAGE TOP VIEW 1DIR[ 1CAB[ 1SAB[ gnd[ 1A1 [ 1A2[ • Independent Registers for A and B Buses

54AC16646

Abstract: 74AC16646 j1b4
Contextual Info: 54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0189— D3477, MARCH 1990 Member of the Texas Instruments Wldebus Family S4AC16646 . . . W D PACKAGE 74AC16646 . . . DL PACKAGE TOP VIEW Packaged in Shrink Small-Outline 300-mil

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

D3402

Abstract: 74ACT16245
Contextual Info: 54ACT16245, 74ACT16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0182— D3402, DECEMBER 1989— REVISED MARCH 1990 54ACT16245 . . . WD PACKAGE 74ACT16245 . . . DL PACKAGE Members of the Texas Instruments Widebus Family TOP VIEW Packaged in Shrink Small Outline 300-mil

74ACT11086

Contextual Info: 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES T 10185— D3390, N O VEM BER 1969 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout TOP VIEW

Contextual Info: 54ACT11377, 74ACT11377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE T I0 186— D3450, MARCH 1990 54ACT11377 . . . JT PACKAGE 74ACT11377 . . . DW or NT PACKAGE • Inputs are TTL-Voltage Compatible • Contains Eight D-Type Flip-Flops TOP VIEW • Clock Enable Latched to Avoid False

2A337

Abstract: 74AC16244
Contextual Info: 54AC16244, 74AC16244 16-BIT BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0180— 0 3 4 6 5 , MARCH 1990 54A C 16244 . . . WO PACKAGE 74AC16244 . . . DL PACKAGE Member of the Texas Instruments Widebus’* Family TOP VIEW Packaged in Shrink Small Outline 300-mil

74AC11873

Contextual Info: TEXAS INSTR LOGIC 31E 3> ^ , 1/ 1 2 3 o a a ^ a s D a 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS ,v , 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture to Optimize PCB Layout 7 _T10167— D3398, MARCH 1990

74ACT11086

Abstract: MIK 494 T-43-21 TTO185 D3330
Contextual Info: TEXAS INSTR LOGIC 31E D 0^1723 QGÔÔ534 3 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES T 'Ì 3 'Z 4 ~ o O N O VEM B ER 1989 T O 185— D 3390, NOVEI* • Inputs are TTL-Voltage Compatible 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE

Contextual Info: 54ACT16646, 74ACT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0169— D347B. MARCH 1990 Member of the Texas Instruments Widebus Family 54ACT16646 . . . WD PACKAGE 74ACT16646 . . . DL PACKAGE TOP VIEW Packaged in Shrink Smali-Outiine 300-mll

T118B

Abstract: T118B1 TIO10A 0A028
Contextual Info: 54ACT11881, 74ACT11881 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0188— D3480, MARCH 1900 Inputs are TTL-Voltage Compatible 54ACT11881 . . . JT OR JW PACKAGE 74ACT11881 . . . DW OR NT PACKAGE • Full Look-Ahead for High-Speed Operations on Long Words