54LS11 Search Results

Contextual Info: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE

Contextual Info: TYPES SN54H11, 54LS11, SN54S11, SN74H11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES R E V IS E D A P R IL 1 S 8 5 Dependable Texas Instruments Quality and Reliability SN54H11 . . . J PACKAGE SN 54LS11, SN 54 S1 1 . . . J OR W PACKAGE SN 74H11 . . . J OR N PACKAGE

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

54LS113

Contextual Info: LS113 H t] National Juâ Semiconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may

Contextual Info: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

CP12A-1

Contextual Info: M MOTOROLA M ilitary 54LS112A D u a l J -K Flip-Flop W ith C le a r an d Pre se t ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asyn­ chronous set and clear inputs to each flip-flop. When the clock goes

Contextual Info: M M O T O R O L A Military 54LS114A D u a l J -K Flip-Flop W ith Preset, C o m m o n C le ar and C o m m o n C lo c k MIL-M-38510/30105 T h e 5 4 L S 1 1 4 A o ffe rs c o m m o n clock a n d c o m m o n clear inputs and in d ivid u al J, K, and set inputs. Th e se m o n o lith ic dual flip -flo p s are

Contextual Info: M ilita ry 5 4 L S 1 1 <8> M O T O R O L A Triple 3-Input P ositive AND G ate MP0 m ini ELECTRICALLY TESTED PER: MIL-M-38510/31001 LOGIC DIAGRAM Vcc C1 Y1 C3 B3 A3 Y3 AVAILABLE AS: 1 JAN: JM38510/31001BXA 2) SMD: N/A 3)883: 54LS11/BXAJC X = CASE OUTLINE AS FOLLOWS:

Contextual Info: 54LS11,54LS11,DM74LS11 54LS11 54LS11 DM74LS11 Triple 3-Input AND Gates Literature Number: SNOS279A 54LS11 54LS11 DM74LS11 Triple 3-Input AND Gates General Description Features This device contains three independent gates each of which performs the logic AND function

Contextual Info: S E M IC O N D U C T O R tm DM74LS11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic A N D function. Features • Alternate m ilitary/aerospace device 54LS11 is available. C ontact a Fairchild Sem iconductor Sales

74LS11

Abstract: 74S11 54ls11
Contextual Info: S N 54LS11, SN54S11, SN 74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE AND GATES A PRIL 19 85 —R EV ISED MARCH 1988 S N 5 4 L S 1 1 . S N 7 4 S 1 1 . . . J OR W P A C K A G E SN 74LS11. SN 74S11 c 1 U 14 : 13 : 2 12 q 3 11 : c4 10 c 5 9 : c6 1A c IB Dependable Texas Instruments Quality and

Contextual Info: 8 < > M ilitary 54LS114A MOTOROLA Dual J -K Flip-Flop W ith P reset, Common C lear and Com m on C lock MPO MIL-M-38510/30105 unw The 54LS114A offers common clock and common clear inputs and individual J, K, and set Inputs. These monolithic dual flip-flops are

Contextual Info: & > M ilitary 54LS112A MOTOROLA Dual J -K Flip-Flop W ith C lear and P reset lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30103 M PO The 54LS112A dual flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes

dm74ls112an

Abstract: 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112A DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM
Contextual Info: 54LS112 54LS112A DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and

LS114

Contextual Info: ^ National Semiconductor 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’L S 1 14 features individual J, K and set inputs and com­ mon clock and common clear inputs. When the clock goes HIGH the inputs are enabled and data will be accepted. The

54ls11

Contextual Info: June 1989 54LS11/54LS11/DM74LS11 Triple 3-Input AND Gates General Description Features This device contains three independent gates each of which performs the logic AND function. • Alternate military/aerospace device 54LS11 is available. Contact a National Semiconductor Sales Office/

Contextual Info: & June 1989 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

SN54LS114A

Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
Contextual Info: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation

54LS113

Abstract: 54LS 54LS113DMQB 54LS113FMQB 54LS113LMQB C1995 E20A J14A W14B
Contextual Info: 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the bistable

Contextual Info: LS11 01 National itiI Semiconductor 54LS11/54LS11/DM74LS11 Triple 3-Input AND Gates General Description Features This device contains three independent gates each of which performs the logic AND function. • Alternate military/aerospace device 54LS11 is avail­

Contextual Info: M M O T O R O M ilitary 54LS114A L A Dual J -K Flip-Flop W ith P reset, Com m on C lear and Com m on C lock M MIL-M-38510/30105 P O H U M The 54LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are

Contextual Info: LS113 National J j I Semiconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may

Contextual Info: S E M IC O N D U C T O R tm DM74LS11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic AN D function. Features • Alternate m ilitary/aerospace device 54LS11 is available. C ontact a Fairchild Sem iconductor Sales

Contextual Info: M O TO R O LA Military 54LS11 Triple 3-Input Positive AND Gate ELECTRICALLY TESTED PER: MIL-M-38510/31001 LOGIC DIAGRAM V cc ci VI C3 B3 AVAILABLE AS . A3 « 1 JA N : JM 38510/31001BXA 2) SM D: * 3) 883C: 54LS11/BXAJC i*r r 41 X = CASE O UTUNE AS FOLLOWS: