54LS74 Search Results

Contextual Info: ^ M O T O R O L A M ilitary 5 4 LS7 4 A D u a l D -Type Flip-Flop W ith C le a r and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30102 The 54LS74A dual e dg e -trig ge re d flip -flo p u tilizes S chottky TTL c irc u i­ try to produce high-speed D -type flip -flo p s . Each flip -flo p has in d iv id u a l

DM74LS74A

Contextual Info: 54LS74,54LS74A,DM74LS74A 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Literature Number: SNOS313A 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs

DM74LS74AN

Contextual Info: LS74A National ÉSA Semiconductor 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

54LS74

Contextual Info: LS74A National Semiconductor 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

DM74LS74AN

Abstract: 54LS74 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74AJ DM54LS74AW DM74LS74AM E20A 074d
Contextual Info: June 1989 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered D flip-flops with complementary outputs. The informa­

Contextual Info: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a

Contextual Info: & June 1989 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered D flip-flops with complementary outputs. The informa­

54LS74A

Contextual Info: M ilita ry 54L S 74A MOTOROLA Dual D-iype Flip-Flop W ith C le ar and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30102 M The 54LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high-speed D-type flip-flops. Each flip-flop has

MAB08

Abstract: DM74LS74AN 54LS74 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74A DM54LS74AJ DM54LS74AW DM74LS74A
Contextual Info: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a

Contextual Info: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description violated A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

Contextual Info: M MOTOROLA M ilitary 54LS74A Dual D -iype Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30102 H T h e 54LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high-speed D-type flip-flops. Each flip-flop has

54LS74A

Abstract: Di801 max5539 54S74
Contextual Info: Signetics 54LS74A, 54S74 Flip-Flops Dual D-Type Flip-Flops Product Specification Military Logic Products DESCRIPTION The 54LS7 4 A , 5 4 S 7 4 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, Set and R eset in­ puts; also com plem entary Q and O out­

74ls74a ic

Abstract: SN54L74
Contextual Info: TYPES SN5474, SN54H74, SN54L74, 54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR R E V IS E D D E C E M B E R 1983 Package Options Include Both Plástic and Ceram ic Chip Carriers in Addition to Plastic

F7474PC

Abstract: 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D 7474PC IC 74LS74 pin IC 7474 74LS74PC IC 7474 flipflop
Contextual Info: 74 C O N N E C T IO N DIAGRAM S P IN O U T A 54/7474 < ? / / 6 ' \/54H/74H74 t f e. j w w^4S/74S74 £>/, o 'b, U34LS/74LS74 ^ ^ < - 3 ^ — "Si / / DUAL D-TYPE POSITIVE ED G e"TRIGGERED FLIP-FLOP P IN O U T B DESCRIPTIO N — The ’74 devices are dual D-type flip-flops with Direct C le a r

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

74ls169 motorola

Abstract: 8 decade counter
Contextual Info: g MOTOROLA SN54LS/74LS168 SN54LS/74LS169 D E S C R IP T IO N — Th eS N 54LS /7 4LS 16 8and S N 5 4LS /74 LS 169 are fully synchronous 4-stage u p /d o w n counters featuring a preset capability for programmable operation, carry lookahead for easy cas­

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

54LS641

Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
Contextual Info: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the

bipolar PROM

Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
Contextual Info: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415

Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 04/23/98 Last Update Date: 08/24/98 Last Major Revision Date: 04/23/98 54LS74-X REV 1A0 DUAL POSITIVE EDGE-TRIGGERED D FLIP-FLOPS with PRESET, CLEAR and COMPLEMENTARY OUTPUTS General Description The 'LS74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary

7474PC

Abstract: 74LS74PC 74h74p 74LS74DC 74ls74D 7474 truth table 74H74D 7474 D flip-flop 7474 pin out diagram 74H74DC
Contextual Info: 74 CONNECTIO N DIAGRAMS PINOUT A 54/7474 < 2 y / 6 ‘ V/S4H/74H74 û / / ^S4S/74S74 0 / / 5 3 s 54L S /74L S 74 { / / i ; = DUAL D-TYPE POSITIVE EDGETRIGGERED FLIP-FLOP D DESCRIPTION — T h e '74 devices are dual D-type flip -flop s with Direct Clear and Set inputs and com plem entary Q, Q outputs. Inform ation at the input is

SN74574

Abstract: SN7457 sn7474 SN5474 SN54LS74A SN54S74 SN74 SN74LS74A SN74S74
Contextual Info: SN5474, 54LS74A, SN54S74, SN7474, SN74LS74A, SN74S74 SDLS119 DUAL 0-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1 9 B 3 - Package Options Include Plastic "Small Outline" Packages. Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic