54HCTLS Search Results

74HCTLS

Abstract: el 519
Contextual Info: Zyfi vx ZXS4HCTLS Ë U ZX74HCTLS Ê February 1985 T r ip le 3 -In p u t N A N D E G a te ^ OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input NAND

F4049

Abstract: 74HCTLS 0100L HCTL
Contextual Info: fytrox iîsi 3 7 3 February 1985 Octal D-Type Transparent Latches with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • 8 latches in a single package The '373 consists of 8 high-speed D-type latches cou­ pled to 3-state output buffers with high drive current ca­

74HCTLS

Contextual Info: Zvtrex 54HCTLS ZX74HCTLS February 1985 78A Dual J-K Flip-Flops with Preset, Common Clear & Common Clock O B J E C T IV E SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These parts consist of two oegatjye-edge-triggered J-K

Zytrex

Abstract: 74HCTLS
Contextual Info: iVfrex . ZX 54 HC TL S _ _ ZX 74 HC TL S February 1985 # S a m m # M Monostable Multivibrators with Schmitt- Trigger Inputs OBJECTIVE SPECIFICATIONS Features Description • Schmitt-trigger for slow Input transitions Th ese m u ltivib ra to rs fea ture du al ne ga tive -tra n sitio n -trig ­

Zytrex quad and gate

Abstract: 74hctls
Contextual Info: Z y tr c x _ February1985 08 Quad 2-Input AND Gâté# / OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input AND gates. They perform the Boolean functions Y = A • B or

74HCTLS

Contextual Info: Z y tr e x 54HCTLS M ZX74HCTLS M February 1985 M Hex Schmitt-Trigger Inverters OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74LS logic family These Schm itt-trigger devices contain six independent

74hctls

Contextual Info: Zytrex 54HCTLS ZX74HCTLS no f M^ Quad 2-Input NOR Gates February 1905 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These d e vice s con tain fo u r in d e p e n d e n t 2 -in put N O R

74hctls

Contextual Info: Zytrex 54HCTLS ZX74HCTLS 73A Dual J-K Negative-Edge-Triggered Flip-Flops with Clear Februa ry 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the CLR input

Contextual Info: 1 S A M S U N G S E M I C O N D U C T O R INC OE D ElTTL^m a 5181519 KS74HCTLS 520/521/522 000t,S23 7 8-Bit Identity Comparators FEATURES DESCRIPTION • Compares two 8-bit words • ’518, ’520 and ’522 have 20KR Pull-up resistors on Q Inputs These identity comparators perform comparisons on two

74HCTLS

Abstract: 54HCTLS
Contextual Info: 365A/367A %%%%366A /368A ZXS4HCTLS ZX74HC TLS 1 Hex Bus-Drivers with 3-State Outputs February 1985 O B JE C TIV E S P E C IF IC A T IO N S Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These high-speed Hex bus drivers are designed specifi­

74HCTLS

Contextual Info: Zytrex 54HCTLS ZX74HCTLS February 1985 273 Octal D-Type Flip-Flops with Clear OBJECTIVE SPECIFICATIONS Features Description • Eight positive-edge-triggered D-type flipflops with single-rail outputs these devices are high-speed octal registers. They con­

74hctls

Contextual Info: Z y tre x _ %%%&259 February 1985 8-Bit Addressable Latches OBJECTIVE SPECIFICATIONS Features Description • 8-Bit parallel-out storage register performs serial-to-parallel conversion with storage The '259 is a high-speed addressable latch designed for

74LS TTL 245

Abstract: 74HCTLS 74hctl PPT Diode specifications
Contextual Info: Zytrex 54HCTLS ZX74HCTLS February 1985 245 Octal Bus Transceivers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These high-speed octal bus transceivers are designed

74HCTLS

Contextual Info: Zvtrex 54HCTLS ZX74HCTLS 138 3-Line to 8-Line Decoders/Multiplexers February 1985 OBJECTIVE SPECIFICATIONS Features Description m Designed specifically for high-speed memory These devices are designed to be used in high-perform ­ ance m em ory-decoding or data-routing applications re­

74HCTLS

Abstract: and cmos Zytrex
Contextual Info: Zvtrex 54HCTLS Æ ZX74HCTLS F e b ru a ry 1985 i S m^ Dual Retriggerable Monostable Multivibrator OBJECTIVE SPECIFICATIONS Features Description • Simple pulse width formula T = RC The '423 contains two retriggerable monostable multivi­ brators that feature both a negative, A, and a positive, B,

HCTLS

Abstract: 74hctls
Contextual Info: Z v t n 54HCTLS M ZX74HCTLS x February 1985 Quad 2-Input AND Gates with Open-Drain Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-Input AND

74hctls

Contextual Info: Zvtrex ZXS4HCTLS ZX74HCTLS 257 %æ&258 Quad 2-Line to 1-Line Data Selector/ Multiplexers with 3-State Outputs February 1985 OBJECTIVE SPECIFICATIONS Description Features The '257 and ’258 multiplex signals from four-bit data sources to four-output data lines in bus organized sys­

74HCTLS

Abstract: hctls574 HCTLS
Contextual Info: Zytrex 54HCTLS ZX74HCTLS February 1985 574 Octal D-Type Flip-Flops with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family ■ Low power consumption characteristic of

K413

Abstract: 74HCTLS Zytrex 161
Contextual Info: # MJ Lmm ZXS4HCTLS § ZX74HCTLS M Februa,y1985 t 54HCTLS ZX74HCTLS M Ë m a Ê WÂ À t m Synchronous 4-Bit Binary Counters O B JE C T IV E S P E C IF IC A T IO N S ' * Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family

hctls299

Abstract: 74HCTLS
Contextual Info: Zytrex ZXS4HCTLS ZX74HCTLS February 1985 8-Bit Universal Shift/Storage Registers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Multiplexed I/O ports provides improved bit density These eight-bit universal registers feature multiplexed

74HCTLS

Contextual Info: Z v tre x 54HCTLS § ZX74HCTLS M 8-Bit Parallel-ln/Serial-Out Shift Registers with Clear February 1985 OBJECTIVE SPECIFICATIONS Features Description • Synchronous load These devices feature parallel-in or serial-in, serial-out registers, gated clock inputs and an overriding clear in­

74hctls

Abstract: Zytrex OR gate
Contextual Info: Z v t r e ZXS4HCTLS ZX74HCTLS x _ K A Quad 2-Input OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, ptn-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input OR gates. They perform the Boolean functions Y = A + B

74HCTLS

Abstract: diode sy 171 sy 171 74hctl
Contextual Info: Z v tr e ZXS4HCTLS ZX74HCTLS x 6 4 z x k h c t ls 6 4 3 Octal Bus Transceivers February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These high-speed octal bus transceivers are designed

74HCTLS

Contextual Info: Zytrex ZXS4HCTLS ZX74HCTLS Februa ry 1985 74A Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent positive-edgetriggered D-type flip-flops. Each flip-flop has its own